| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 78 reg = ArmManagedRegister::FromSRegister(S1); in TEST()
85 EXPECT_EQ(S1, reg.AsSRegister()); in TEST()
135 EXPECT_EQ(S1, reg.AsOverlappingDRegisterHigh()); in TEST()
312 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
322 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
331 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
336 ArmManagedRegister reg_S1 = ArmManagedRegister::FromSRegister(S1); in TEST()
341 EXPECT_TRUE(reg_S1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
465 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
487 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
[all …]
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 181 sreg = Arm64ManagedRegister::FromSRegister(S1); in TEST()
189 EXPECT_EQ(S1, reg.AsOverlappingSRegister()); in TEST()
294 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
310 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
320 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
328 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
332 Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1); in TEST()
338 EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
387 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
409 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
[all …]
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 58 S1 = 1, enumerator
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| D | context_arm.cc | 82 fprs_[S1] = nullptr; in SmashCallerSaves()
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| D | quick_method_frame_info_arm.h | 41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 659 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S1, dest.Int32Value()); in StoreImmediateToThread32()
669 S1, thr_offs.Int32Value()); in StoreStackOffsetToThread32()
673 StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread32()
690 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread32()
722 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread32()
775 S1, thr_offs.Int32Value()); in CopyRawPtrFromThread32()
788 S1, thr_offs.Int32Value()); in CopyRawPtrToThread32()
949 Move(tr.AsMips().AsCoreRegister(), S1); in GetCurrentThread()
954 StoreToOffset(kStoreWord, S1, SP, offset.Int32Value()); in GetCurrentThread()
962 S1, Thread::ExceptionOffset<4>().Int32Value()); in ExceptionPoll()
[all …]
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 47 S1 = 17, enumerator
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| D | quick_method_frame_info_mips.h | 34 (1 << art::mips::S0) | (1 << art::mips::S1);
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 47 S1 = 17, enumerator
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| D | quick_method_frame_info_mips64.h | 37 (1 << art::mips64::S0) | (1 << art::mips64::S1);
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| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 924 __ vmovs(S1, 1.0); in TEST()
927 __ vmovs(S1, S2); in TEST()
942 __ vadds(S0, S1, S2); in TEST()
943 __ vsubs(S0, S1, S2); in TEST()
944 __ vmuls(S0, S1, S2); in TEST()
945 __ vmlas(S0, S1, S2); in TEST()
946 __ vmlss(S0, S1, S2); in TEST()
947 __ vdivs(S0, S1, S2); in TEST()
948 __ vabss(S0, S1); in TEST()
949 __ vnegs(S0, S1); in TEST()
[all …]
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 109 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value()); in CreateTrampoline()
138 __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value()); in CreateTrampoline()
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 155 S1 = 1, enumerator
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| /art/compiler/optimizing/ |
| D | code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
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| D | code_generator_mips64.h | 59 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| D | code_generator_arm.cc | 702 return Location::FpuRegisterPairLocation(S0, S1); in GetReturnLocation()
2343 locations->SetOut(Location::Location::FpuRegisterPairLocation(S0, S1)); in VisitRem()
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| D | code_generator_mips64.cc | 43 static constexpr GpuRegister TR = S1;
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 1205 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, dest.Int32Value()); in StoreImmediateToThread64()
1214 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in StoreStackOffsetToThread64()
1218 StoreToOffset(kStoreDoubleword, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread64()
1235 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread64()
1271 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread64()
1315 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in CopyRawPtrFromThread64()
1327 S1, thr_offs.Int32Value()); in CopyRawPtrToThread64()
1518 Move(tr.AsMips64().AsGpuRegister(), S1); in GetCurrentThread()
1523 StoreToOffset(kStoreDoubleword, S1, SP, offset.Int32Value()); in GetCurrentThread()
1531 S1, Thread::ExceptionOffset<8>().Int32Value()); in ExceptionPoll()
[all …]
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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