| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 130 callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S3)); in Mips64JniCallingConvention()
142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA; in CoreSpillMask()
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 60 S3 = 3, enumerator
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| D | context_arm.cc | 84 fprs_[S3] = nullptr; in SmashCallerSaves()
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| D | quick_method_frame_info_arm.h | 41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 49 S3 = 19, enumerator
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| D | quick_method_frame_info_mips.h | 29 (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | (1 << art::mips::S5) |
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 49 S3 = 19, enumerator
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| D | quick_method_frame_info_mips64.h | 29 (1 << art::mips64::S2) | (1 << art::mips64::S3) | (1 << art::mips64::S4) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 157 S3 = 3, enumerator
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| /art/compiler/optimizing/ |
| D | code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
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| D | code_generator_mips64.h | 59 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 87 reg = ArmManagedRegister::FromSRegister(S3); in TEST()
94 EXPECT_EQ(S3, reg.AsSRegister()); in TEST()
147 EXPECT_EQ(S3, reg.AsOverlappingDRegisterHigh()); in TEST()
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 708 EXPECT_TRUE(vixl::s3.Is(Arm64Assembler::reg_s(S3))); in TEST()
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