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Searched refs:SRegToVReg (Results 1 – 15 of 15) sorted by relevance

/art/compiler/dex/
Dgvn_dead_code_elimination.cc382 if (mir_graph->SRegToVReg(ssa_rep->uses[i]) == v_reg) { in IsVRegUsed()
522 int v_reg = mir_graph_->SRegToVReg(s_reg); in CreatePhi()
566 DCHECK_EQ(mir_graph_->SRegToVReg(new_s_reg) + 1, mir_graph_->SRegToVReg(new_s_reg + 1)); in RenameSRegDefOrCreatePhi()
591 DCHECK_EQ(mir_graph_->SRegToVReg(old_s_reg), mir_graph_->SRegToVReg(new_s_reg)); in RenameSRegDefOrCreatePhi()
630 int v_reg = mir_graph_->SRegToVReg(data->mir->ssa_rep->uses[i]); in BackwardPassProcessLastMIR()
677 old_s_reg, mir_graph_->SRegToVReg(old_s_reg), in RecordPassKillMoveByRenamingSrcDef()
678 new_s_reg, mir_graph_->SRegToVReg(new_s_reg)); in RecordPassKillMoveByRenamingSrcDef()
690 uint32_t src_v_reg = mir_graph_->SRegToVReg(src_s_reg); in RecordPassTryToKillOverwrittenMoveOrMoveSrc()
704 dest_s_reg, mir_graph_->SRegToVReg(dest_s_reg), in RecordPassTryToKillOverwrittenMoveOrMoveSrc()
705 src_s_reg, mir_graph_->SRegToVReg(src_s_reg)); in RecordPassTryToKillOverwrittenMoveOrMoveSrc()
[all …]
Dvreg_analysis.cc72 reg_location_[i].s_reg_low = SRegToVReg(orig_sreg); in RemapRegLocations()
Dmir_optimization.cc700 int def_vreg = SRegToVReg(mir->ssa_rep->defs[0]); in BasicBlockOpt()
1866 int vreg0 = SRegToVReg(second->ssa_rep->defs[0]); in HasAntiDependency()
1868 SRegToVReg(second->ssa_rep->defs[1]) : INVALID_VREG; in HasAntiDependency()
1870 int32_t use = SRegToVReg(first->ssa_rep->uses[i]); in HasAntiDependency()
1923 add_mir->dalvikInsn.vB = SRegToVReg(add_mir->ssa_rep->uses[0]); in CombineMultiplyAdd()
1925 add_mir->dalvikInsn.vC = SRegToVReg(add_mir->ssa_rep->uses[2]); in CombineMultiplyAdd()
1926 add_mir->dalvikInsn.arg[0] = SRegToVReg(add_mir->ssa_rep->uses[4]); in CombineMultiplyAdd()
1928 add_mir->dalvikInsn.vC = SRegToVReg(add_mir->ssa_rep->uses[1]); in CombineMultiplyAdd()
1929 add_mir->dalvikInsn.arg[0] = SRegToVReg(add_mir->ssa_rep->uses[2]); in CombineMultiplyAdd()
Dmir_graph.cc1640 int vreg = SRegToVReg(ssa_reg); in GetSSAName()
1642 return StringPrintf("t%d_%d", SRegToVReg(ssa_reg), GetSSASubscript(ssa_reg)); in GetSSAName()
1644 return StringPrintf("v%d_%d", SRegToVReg(ssa_reg), GetSSASubscript(ssa_reg)); in GetSSAName()
1657 return StringPrintf("v%d_%d#0x%" PRIx64, SRegToVReg(ssa_reg), GetSSASubscript(ssa_reg), in GetSSANameWithConst()
1660 return StringPrintf("v%d_%d#0x%x", SRegToVReg(ssa_reg), GetSSASubscript(ssa_reg), in GetSSANameWithConst()
1664 int vreg = SRegToVReg(ssa_reg); in GetSSANameWithConst()
1666 return StringPrintf("t%d_%d", SRegToVReg(ssa_reg), GetSSASubscript(ssa_reg)); in GetSSANameWithConst()
1668 return StringPrintf("v%d_%d", SRegToVReg(ssa_reg), GetSSASubscript(ssa_reg)); in GetSSANameWithConst()
2373 int dalvik_reg = c_unit->mir_graph->SRegToVReg(ssa_reg); in IsSSALiveOut()
2390 int def_dalvik_reg = c_unit->mir_graph->SRegToVReg(def_ssa_reg); in IsSSALiveOut()
Dgvn_dead_code_elimination_test.cc238 int SRegToVReg(int32_t s_reg, bool wide) { in SRegToVReg() function in art::GvnDeadCodeEliminationTest
239 int v_reg = cu_.mir_graph->SRegToVReg(s_reg); in SRegToVReg()
247 int SRegToVReg(int32_t* uses, size_t* use, bool wide) { in SRegToVReg() function in art::GvnDeadCodeEliminationTest
248 int v_reg = SRegToVReg(uses[*use], wide); in SRegToVReg()
300 mir->dalvikInsn.vA = SRegToVReg(def->defs[0], (df_attrs & DF_A_WIDE) != 0); in DoPrepareMIRs()
310 mir->dalvikInsn.vA = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_A_WIDE) != 0); in DoPrepareMIRs()
313 mir->dalvikInsn.vB = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_B_WIDE) != 0); in DoPrepareMIRs()
316 mir->dalvikInsn.vC = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_C_WIDE) != 0); in DoPrepareMIRs()
Dtype_inference.cc213 int v_reg = mir_graph_->SRegToVReg(s_reg); in AddPseudoPhis()
337 int v_reg = mir_graph_->SRegToVReg(s_reg); in FindDefBlock()
374 DCHECK_EQ(v_reg, mir_graph_->SRegToVReg(s_reg)); in IsSRegLiveAtStart()
Dssa_transformation.cc513 int v_reg = SRegToVReg(ssa_reg); in InsertPhiNodeOperands()
Dmir_graph.h1112 int SRegToVReg(int ssa_reg) const { in SRegToVReg() function
Dlocal_value_numbering.cc531 bool live = live_in_v->IsBitSet(gvn_->GetMirGraph()->SRegToVReg(entry.first)); in CopyLiveSregValues()
554 bool live_and_same = live_in_v->IsBitSet(gvn_->GetMirGraph()->SRegToVReg(entry.first)); in IntersectSregValueMaps()
/art/compiler/dex/quick/
Dgen_loadstore.cc268 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1), in StoreValueWide()
269 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low))); in StoreValueWide()
332 DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1), in StoreFinalValueWide()
333 mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low))); in StoreFinalValueWide()
Dralloc_util.cc253 int v_reg = mir_graph_->SRegToVReg(s_reg); in SRegToPMap()
260 int v_reg = mir_graph_->SRegToVReg(s_reg); in RecordCorePromotion()
293 int v_reg = mir_graph_->SRegToVReg(s_reg); in RecordFpPromotion()
741 if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) { in FlushRegWide()
744 int v_reg = mir_graph_->SRegToVReg(info1->SReg()); in FlushRegWide()
752 int v_reg = mir_graph_->SRegToVReg(info->SReg()); in FlushRegWide()
764 int v_reg = mir_graph_->SRegToVReg(info->SReg()); in FlushReg()
1496 return VRegOffset(mir_graph_->SRegToVReg(s_reg)); in SRegOffset()
Dcodegen_util.cc1248 …return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) … in PartiallyIntersects()
1254 …return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) … in Intersects()
1408 references->SetBit(mir_graph_->SRegToVReg(defs[0])); in UpdateReferenceVRegsLocal()
1411 references->ClearBit(mir_graph_->SRegToVReg(defs[i])); in UpdateReferenceVRegsLocal()
1429 references->SetBit(mir_graph_->SRegToVReg(mir->ssa_rep->uses[0])); in UpdateReferenceVRegs()
/art/compiler/dex/quick/x86/
Dfp_x86.cc632 int v_src_reg = mir_graph_->SRegToVReg(rl_src.s_reg_low); in GenInlinedAbsFloat()
633 int v_dst_reg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); in GenInlinedAbsFloat()
683 int v_src_reg = mir_graph_->SRegToVReg(rl_src.s_reg_low); in GenInlinedAbsDouble()
684 int v_dst_reg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); in GenInlinedAbsDouble()
Dint_x86.cc907 if (mir_graph_->SRegToVReg(rl_src1.s_reg_low) == in GenInlinedMinMax()
908 mir_graph_->SRegToVReg(rl_src2.s_reg_low)) { in GenInlinedMinMax()
1850 bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == in GenMulLong()
1851 mir_graph_->SRegToVReg(rl_src2.s_reg_low); in GenMulLong()
2038 int v_src_reg = mir_graph_->SRegToVReg(rl_src.s_reg_low); in GenLongArith()
2039 int v_dst_reg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); in GenLongArith()
3173 (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == in GenArithOpInt()
3174 mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { in GenArithOpInt()
3280 if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == in GenArithOpInt()
3281 mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { in GenArithOpInt()
/art/compiler/dex/quick/arm/
Dtarget_arm.cc841 int v_reg = mir_graph_->SRegToVReg(s_reg); in AllocPreservedDouble()
894 int v_reg = mir_graph_->SRegToVReg(s_reg); in AllocPreservedSingle()