Searched refs:base_reg (Results 1 – 8 of 8) sorted by relevance
| /art/compiler/dex/quick/arm/ |
| D | assemble_arm.cc | 1318 int base_reg = ((lir->opcode == kThumb2LdrdPcRel8) || in AssembleLIR() local
1324 base_reg, 0, 0, 0, 0, lir->target); in AssembleLIR()
1347 lir->operands[2] = base_reg; in AssembleLIR()
1350 lir->operands[1] = base_reg; in AssembleLIR()
|
| /art/compiler/dex/quick/x86/ |
| D | utility_x86.cc | 945 LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch() argument
948 LIR* inst = NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), in OpCmpMemImmBranch()
|
| D | codegen_x86.h | 814 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
|
| /art/compiler/dex/quick/arm64/ |
| D | codegen_arm64.h | 85 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
|
| D | int_arm64.cc | 301 RegStorage base_reg, int offset, int check_value, in OpCmpMemImmBranch() argument
309 Load32Disp(base_reg, offset, temp_reg); in OpCmpMemImmBranch()
|
| /art/compiler/dex/quick/ |
| D | codegen_util.cc | 1257 LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch() argument
1260 LIR* inst = Load32Disp(base_reg, offset, temp_reg); in OpCmpMemImmBranch()
|
| D | mir_to_lir.h | 1136 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
|
| /art/compiler/dex/ |
| D | local_value_numbering.cc | 1333 int base_reg = (opcode == Instruction::IPUT_WIDE) ? 2 : 1; in HandleIPut() local
1334 uint16_t base = GetOperandValue(mir->ssa_rep->uses[base_reg]); in HandleIPut()
|