/art/runtime/base/ |
D | bit_vector_test.cc | 71 uint32_t bits[kWords]; in TEST() local 72 memset(bits, 0, sizeof(bits)); in TEST() 74 BitVector bv(false, Allocator::GetNoopAllocator(), kWords, bits); in TEST() 77 EXPECT_EQ(bits, bv.GetRawStorage()); in TEST() 128 uint32_t bits[kWords]; in TEST() local 129 memset(bits, 0, sizeof(bits)); in TEST() 131 BitVector bv(false, Allocator::GetNoopAllocator(), kWords, bits); in TEST()
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D | bit_utils.h | 210 static constexpr T GetIntLimit(size_t bits) { in GetIntLimit() argument 212 DCHECK_CONSTEXPR(bits > 0, "bits cannot be zero", 0) in GetIntLimit() 213 DCHECK_CONSTEXPR(bits < BitSizeOf<T>(), "kBits must be < max.", 0) in GetIntLimit() 214 static_cast<T>(1) << (bits - 1); in GetIntLimit() 268 explicit BitIteratorBase(T bits) : bits_(bits) { } in BitIteratorBase() argument 324 IterationRange<LowToHighBitIterator<T>> LowToHighBits(T bits) { in LowToHighBits() argument 326 LowToHighBitIterator<T>(bits), LowToHighBitIterator<T>()); in LowToHighBits() 330 IterationRange<HighToLowBitIterator<T>> HighToLowBits(T bits) { in HighToLowBits() argument 332 HighToLowBitIterator<T>(bits), HighToLowBitIterator<T>()); in HighToLowBits()
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D | bit_vector.h | 129 static constexpr uint32_t BitsToWords(uint32_t bits) { in BitsToWords() argument 130 return RoundUp(bits, kWordBits) / kWordBits; in BitsToWords()
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/art/runtime/ |
D | art_field-inl.h | 216 JValue bits; in GetFloat() local 217 bits.SetI(Get32(object)); in GetFloat() 218 return bits.GetF(); in GetFloat() 224 JValue bits; in SetFloat() local 225 bits.SetF(f); in SetFloat() 226 Set32<kTransactionActive>(object, bits.GetI()); in SetFloat() 231 JValue bits; in GetDouble() local 232 bits.SetJ(Get64(object)); in GetDouble() 233 return bits.GetD(); in GetDouble() 239 JValue bits; in SetDouble() local [all …]
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/art/compiler/dex/quick/arm64/ |
D | utility_arm64.cc | 28 int32_t Arm64Mir2Lir::EncodeImmSingle(uint32_t bits) { in EncodeImmSingle() argument 38 if ((bits & 0x0007ffff) != 0) in EncodeImmSingle() 42 uint32_t b_pattern = (bits >> 16) & 0x3e00; in EncodeImmSingle() 47 if (((bits ^ (bits << 1)) & 0x40000000) == 0) in EncodeImmSingle() 52 uint32_t bit7 = ((bits >> 31) & 0x1) << 7; in EncodeImmSingle() 54 uint32_t bit6 = ((bits >> 29) & 0x1) << 6; in EncodeImmSingle() 56 uint32_t bit5_to_0 = (bits >> 19) & 0x3f; in EncodeImmSingle() 60 int32_t Arm64Mir2Lir::EncodeImmDouble(uint64_t bits) { in EncodeImmDouble() argument 71 if ((bits & UINT64_C(0xffffffffffff)) != 0) in EncodeImmDouble() 75 uint32_t b_pattern = (bits >> 48) & 0x3fc0; in EncodeImmDouble() [all …]
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D | assemble_arm64.cc | 703 uint32_t bits = opcode_is_wide ? encoder->xskeleton : encoder->wskeleton; in EncodeLIRs() local 807 bits |= value; in EncodeLIRs() 821 bits |= value; in EncodeLIRs() 826 bits |= value; in EncodeLIRs() 831 bits |= value; in EncodeLIRs() 841 write_pos[0] = (bits & 0xff); in EncodeLIRs() 842 write_pos[1] = ((bits >> 8) & 0xff); in EncodeLIRs() 843 write_pos[2] = ((bits >> 16) & 0xff); in EncodeLIRs() 844 write_pos[3] = ((bits >> 24) & 0xff); in EncodeLIRs()
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D | target_arm64.cc | 307 uint64_t bits = bit_mask(imm_s + 1); in DecodeLogicalImmediate() local 308 return RotateRight(bits, imm_r, 64); in DecodeLogicalImmediate() 315 uint64_t bits = bit_mask((imm_s & mask) + 1); in DecodeLogicalImmediate() local 316 return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); in DecodeLogicalImmediate()
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D | codegen_arm64.h | 340 int32_t EncodeImmSingle(uint32_t bits); 341 int32_t EncodeImmDouble(uint64_t bits);
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/art/compiler/dex/quick/arm/ |
D | assemble_arm.cc | 1102 uint32_t bits = encoder->skeleton; in EncodeLIRs() local 1111 bits |= value; in EncodeLIRs() 1117 bits |= value; in EncodeLIRs() 1118 DCHECK_EQ((bits & (1 << 13)), 0u); in EncodeLIRs() 1123 bits |= value; in EncodeLIRs() 1124 DCHECK_EQ((bits & (1 << 13)), 0u); in EncodeLIRs() 1125 DCHECK_EQ((bits & (1 << 15)), 0u); in EncodeLIRs() 1135 bits |= value; in EncodeLIRs() 1143 bits |= value; in EncodeLIRs() 1148 bits |= value; in EncodeLIRs() [all …]
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D | target_arm.cc | 331 uint32_t bits = value & 0xff; in ExpandImmediate() local 334 return bits; in ExpandImmediate() 336 return (bits << 16) | bits; in ExpandImmediate() 338 return (bits << 24) | (bits << 8); in ExpandImmediate() 340 return (bits << 24) | (bits << 16) | (bits << 8) | bits; in ExpandImmediate() 344 bits = (bits | 0x80) << 24; in ExpandImmediate() 345 return bits >> (((value & 0xf80) >> 7) - 8); in ExpandImmediate()
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/art/compiler/dex/quick/mips/ |
D | README.mips | 25 The resource masks in the LIR structure are 64-bits wide, which is enough 32 o The Arm target uses 52 of the 64 bits, so we could support float 34 o We could likely assign the 4 non-register bits (kDalvikReg, kLiteral, 36 don't need def/use bits because they are never modified by code
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D | assemble_mips.cc | 792 uint32_t bits = encoder->skeleton; in AssembleInstructions() local 808 bits |= value; in AssembleInstructions() 812 bits |= (value << encoder->field_loc[i].start); in AssembleInstructions() 813 bits |= (value << encoder->field_loc[i].end); in AssembleInstructions() 823 bits |= value; in AssembleInstructions() 830 bits |= value; in AssembleInstructions() 837 code_buffer_.push_back(bits & 0xff); in AssembleInstructions() 838 code_buffer_.push_back((bits >> 8) & 0xff); in AssembleInstructions() 839 code_buffer_.push_back((bits >> 16) & 0xff); in AssembleInstructions() 840 code_buffer_.push_back((bits >> 24) & 0xff); in AssembleInstructions()
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/art/test/436-shift-constant/ |
D | info.txt | 1 Regression tests for shift instructions and constants larger than 8bits.
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/art/test/419-long-parameter/ |
D | info.txt | 2 on 32bits architectures. The move to hard float ABI makes it so that the
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/art/runtime/arch/arm/ |
D | quick_entrypoints_arm.S | 473 and r3, #LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED @ zero the read barrier bits 489 and r3, #LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED @ zero the read barrier bits. 491 …lsr r3, r2, LOCK_WORD_READ_BARRIER_STATE_SHIFT @ if either of the upper two bits (28-29) are s… 494 strex r3, r2, [r0, #MIRROR_OBJECT_LOCK_WORD_OFFSET] @ strex necessary for read barrier bits 522 cbnz r2, .Lslow_unlock @ if either of the top two bits are set, go slow path 525 and r3, #LOCK_WORD_READ_BARRIER_STATE_MASK_TOGGLED @ zero the read barrier bits 527 uxth r3, r3 @ zero top 16 bits
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