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Searched refs:d5 (Results 1 – 11 of 11) sorted by relevance

/art/test/705-register-conflict/src/
DMain.java28 double d0 = 0, d1 = 0, d2 = 0, d3 = 0, d4 = 0, d5 = 0, d6 = 0, d7 = 0; in $opt$registerConflictTest() local
38 d5 = d4 + 1; in $opt$registerConflictTest()
39 d6 = d5 + 1; in $opt$registerConflictTest()
68 return d0 + d1 + d2 + d3 + d4 + d5 + d6 + d7 in $opt$registerConflictTest()
/art/runtime/arch/arm64/
Djni_entrypoints_arm64.S30 stp d4, d5, [sp, #-16]!
48 ldp d4, d5, [sp], #16
Dquick_entrypoints_arm64.S212 stp d4, d5, [sp, #40]
302 ldp d4, d5, [sp, #40]
809 LOADREG x15 8 d5 .LfillRegisters
934 LOADREG x15 8 d5 .LfillRegisters2
955 ldp d4, d5, [x1], #16
1594 ldp d4, d5, [sp, #96]
/art/test/703-floating-point-div/src/
DMain.java39 double d5 = Double.POSITIVE_INFINITY; in divDoubleTest() local
50 expectEquals(Double.doubleToRawLongBits(dPi/d5), 0x0L); in divDoubleTest()
/art/test/080-oom-throw/src/
DMain.java40 double d1, d2, d3, d4, d5, d6, d7, d8; // Bloat this object so we fill the heap faster. field in Main.InstanceMemEater
/art/compiler/optimizing/
Dcode_generator_arm64.h43 vixl::d0, vixl::d1, vixl::d2, vixl::d3, vixl::d4, vixl::d5, vixl::d6, vixl::d7
85 { vixl::d0, vixl::d1, vixl::d2, vixl::d3, vixl::d4, vixl::d5, vixl::d6, vixl::d7 };
/art/test/800-smali/smali/
Db_22881413.smali21 .field private static unres5:La/b/c/d5;
220 sget-object v0, LB22881413;->unres5:La/b/c/d5;
/art/test/700-LoadArgRegs/src/
DMain.java273 …static void testMore(int i1, double d1, double d2, double d3, double d4, double d5, double d6, dou… in testMore() argument
274 …System.out.println(i1+", "+d1+", "+d2+", "+d3+", "+d4+", "+d5+", "+d6+", "+d7+", "+d8+", "+d9+", "… in testMore()
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc676 EXPECT_TRUE(vixl::d5.Is(Arm64Assembler::reg_d(D5))); in TEST()
/art/test/083-compiler-regressions/src/
DMain.java5349 double d5 = 5; in largeFrameFloat() local
7347 d5 = d4; in largeFrameFloat()
7349 d6 = d5; in largeFrameFloat()
/art/compiler/utils/
Dassembler_thumb_test_expected.cc.inc483 " 4: ed2d 2b08 vpush {d2-d5}\n",
485 " c: ecbd 2b08 vpop {d2-d5}\n",