Searched refs:fpu_spill_mask_ (Results 1 – 3 of 3) sorted by relevance
173 uint32_t GetFpuSpillMask() const { return fpu_spill_mask_; } in GetFpuSpillMask()182 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()344 fpu_spill_mask_(0), in CodeGenerator()386 return POPCOUNT(fpu_spill_mask_) * GetFloatingPointSpillSlotSize(); in GetFpuSpillSize()415 uint32_t fpu_spill_mask_; variable
503 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()508 if (fpu_spill_mask_ != 0) { in ComputeSpillMask()509 uint32_t least_significant_bit = LeastSignificantBit(fpu_spill_mask_); in ComputeSpillMask()510 uint32_t most_significant_bit = MostSignificantBit(fpu_spill_mask_); in ComputeSpillMask()512 fpu_spill_mask_ |= (1 << i); in ComputeSpillMask()547 if (fpu_spill_mask_ != 0) { in GenerateFrameEntry()548 SRegister start_register = SRegister(LeastSignificantBit(fpu_spill_mask_)); in GenerateFrameEntry()549 __ vpushs(start_register, POPCOUNT(fpu_spill_mask_)); in GenerateFrameEntry()550 __ cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(fpu_spill_mask_)); in GenerateFrameEntry()551 __ cfi().RelOffsetForMany(DWARFReg(S0), 0, fpu_spill_mask_, kArmWordSize); in GenerateFrameEntry()[all …]
239 fpu_spill_mask_); in GetFramePreservedFPRegisters()