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Searched refs:imm (Results 1 – 25 of 32) sorted by relevance

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/art/compiler/utils/x86/
Dassembler_x86.h221 void pushl(const Immediate& imm);
231 void movl(const Address& dst, const Immediate& imm);
242 void movb(const Address& dst, const Immediate& imm);
250 void movw(const Address& dst, const Immediate& imm);
315 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
316 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
365 void cmpw(const Address& address, const Immediate& imm);
367 void cmpl(Register reg, const Immediate& imm);
372 void cmpl(const Address& address, const Immediate& imm);
375 void testl(Register reg, const Immediate& imm);
[all …]
Dassembler_x86.cc81 void X86Assembler::pushl(const Immediate& imm) { in pushl() argument
83 if (imm.is_int8()) { in pushl()
85 EmitUint8(imm.value() & 0xFF); in pushl()
88 EmitImmediate(imm); in pushl()
106 void X86Assembler::movl(Register dst, const Immediate& imm) { in movl() argument
109 EmitImmediate(imm); in movl()
134 void X86Assembler::movl(const Address& dst, const Immediate& imm) { in movl() argument
138 EmitImmediate(imm); in movl()
198 void X86Assembler::movb(const Address& dst, const Immediate& imm) { in movb() argument
202 CHECK(imm.is_int8()); in movb()
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/art/compiler/utils/x86_64/
Dassembler_x86_64.cc78 void X86_64Assembler::pushq(const Immediate& imm) { in pushq() argument
80 CHECK(imm.is_int32()); // pushq only supports 32b immediate. in pushq()
81 if (imm.is_int8()) { in pushq()
83 EmitUint8(imm.value() & 0xFF); in pushq()
86 EmitImmediate(imm); in pushq()
106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { in movq() argument
108 if (imm.is_int32()) { in movq()
113 EmitInt32(static_cast<int32_t>(imm.value())); in movq()
117 EmitInt64(imm.value()); in movq()
122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { in movl() argument
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Dassembler_x86_64.h319 void pushq(const Immediate& imm);
334 void movl(const Address& dst, const Immediate& imm);
345 void movb(const Address& dst, const Immediate& imm);
353 void movw(const Address& dst, const Immediate& imm);
425 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
426 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
475 void cmpw(const Address& address, const Immediate& imm);
477 void cmpl(CpuRegister reg, const Immediate& imm);
481 void cmpl(const Address& address, const Immediate& imm);
484 void cmpq(CpuRegister reg0, const Immediate& imm);
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Dassembler_x86_64_test.cc108 x86_64::Immediate imm(value); in TEST() local
109 EXPECT_FALSE(imm.is_int8()); in TEST()
110 EXPECT_FALSE(imm.is_int16()); in TEST()
111 EXPECT_FALSE(imm.is_int32()); in TEST()
/art/compiler/dex/quick/x86/
Dassemble_x86.cc306 arr, arr_kind, arr_flags, imm, \ argument
309 … reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opna…
310 …ore | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opna…
311 …ore | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opna…
312 … reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opn…
313 …ore | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opn…
314 …ore | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opn…
315 … reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opn…
316 …ore | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opn…
317 …ore | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opn…
[all …]
Dcodegen_x86.h451 void EmitImm(const X86EncodingMap* entry, int64_t imm);
464 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm);
466 int32_t raw_disp, int32_t imm);
469 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm);
471 int32_t imm);
473 int32_t imm);
474 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm);
475 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm);
476 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm);
477 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm);
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Dint_x86.cc607 int imm, bool is_div) { in GenDivRemLit() argument
611 if (imm == 1) { in GenDivRemLit()
620 } else if (imm == -1) { // handle 0x80000000 / -1 special case. in GenDivRemLit()
643 } else if (is_div && IsPowerOfTwo(std::abs(imm))) { in GenDivRemLit()
659 NewLIR3(kX86Lea32RM, rl_result.reg.GetReg(), rl_src.reg.GetReg(), std::abs(imm) - 1); in GenDivRemLit()
662 int shift_amount = CTZ(imm); in GenDivRemLit()
664 if (imm < 0) { in GenDivRemLit()
669 CHECK(imm <= -2 || imm >= 2); in GenDivRemLit()
675 CalculateMagicAndShift((int64_t)imm, magic, shift, false /* is_long */); in GenDivRemLit()
722 if (imm > 0 && magic < 0) { in GenDivRemLit()
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Dtarget_x86.cc1828 int imm = mir->dalvikInsn.vB; in GenShiftByteVector() local
1829 if (imm >= 8) { in GenShiftByteVector()
1835 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); in GenShiftByteVector()
1843 uint8_t byte_mask = 0xFF << imm; in GenShiftByteVector()
1858 int imm = mir->dalvikInsn.vB; in GenShiftLeftVector() local
1879 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); in GenShiftLeftVector()
1887 int imm = mir->dalvikInsn.vB; in GenSignedShiftRightVector() local
1907 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); in GenSignedShiftRightVector()
1915 int imm = mir->dalvikInsn.vB; in GenUnsignedShiftRightVector() local
1936 NewLIR2(opcode, rs_dest_src1.GetReg(), imm); in GenUnsignedShiftRightVector()
/art/compiler/utils/
Dassembler_test.h183 for (int64_t imm : imms) { variable
184 Imm new_imm = CreateImmediate(imm);
191 sreg << imm;
423 for (int64_t imm : imms) { in RepeatTemplatedRegistersImm() local
424 Imm new_imm = CreateImmediate(imm); in RepeatTemplatedRegistersImm()
443 sreg << imm; in RepeatTemplatedRegistersImm()
516 for (int64_t imm : imms) { in RepeatRegisterImm() local
517 Imm new_imm = CreateImmediate(imm); in RepeatRegisterImm()
530 sreg << imm; in RepeatRegisterImm()
Dassembler.cc135 uint32_t imm ATTRIBUTE_UNUSED, in StoreImmediateToThread32()
141 uint32_t imm ATTRIBUTE_UNUSED, in StoreImmediateToThread64()
Dassembler.h410 virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm,
413 virtual void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm,
415 virtual void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
/art/compiler/linker/arm/
Drelative_patcher_thumb2.cc70 uint32_t imm = (diff16 >> 11) & 0x1u; in PatchDexCacheReference() local
73 insn = (insn & 0xfbf08f00u) | (imm << 26) | (imm4 << 16) | (imm3 << 12) | imm8; in PatchDexCacheReference()
/art/compiler/optimizing/
Dcode_generator_x86_64.cc700 Immediate imm(GetInt32ValueOf(const_to_move)); in Move() local
702 __ movl(location.AsRegister<CpuRegister>(), imm); in Move()
704 __ movl(Address(CpuRegister(RSP), location.GetStackIndex()), imm); in Move()
2234 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue()); in VisitSub() local
2235 __ subl(first.AsRegister<CpuRegister>(), imm); in VisitSub()
2329 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue()); in VisitMul() local
2330 __ imull(first.AsRegister<CpuRegister>(), imm); in VisitMul()
2471 int64_t imm = Int64FromConstant(second.GetConstant()); in DivRemOneOrMinusOne() local
2473 DCHECK(imm == 1 || imm == -1); in DivRemOneOrMinusOne()
2481 if (imm == -1) { in DivRemOneOrMinusOne()
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Dcode_generator_x86.cc727 Immediate imm(GetInt32ValueOf(const_to_move)); in Move() local
729 __ movl(location.AsRegister<Register>(), imm); in Move()
731 __ movl(Address(ESP, location.GetStackIndex()), imm); in Move()
2132 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue()); in VisitMul() local
2133 __ imull(first.AsRegister<Register>(), imm); in VisitMul()
2343 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); in DivRemOneOrMinusOne() local
2345 DCHECK(imm == 1 || imm == -1); in DivRemOneOrMinusOne()
2351 if (imm == -1) { in DivRemOneOrMinusOne()
2363 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); in DivByPowerOfTwo() local
2365 DCHECK(IsPowerOfTwo(std::abs(imm))); in DivByPowerOfTwo()
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/art/compiler/utils/mips/
Dassembler_mips.h174 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE;
176 void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister mscratch)
272 void EmitI(int opcode, Register rs, Register rt, uint16_t imm);
275 void EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm);
Dassembler_mips.cc55 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { in EmitI() argument
61 imm; in EmitI()
84 void MipsAssembler::EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm) { in EmitFI() argument
89 imm; in EmitFI()
646 void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, in StoreImmediateToFrame() argument
650 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToFrame()
654 void MipsAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, in StoreImmediateToThread32() argument
658 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToThread32()
/art/compiler/utils/mips64/
Dassembler_mips64.h247 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE;
249 void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
345 void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm);
349 void EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm);
Dassembler_mips64.cc47 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI() argument
53 imm; in EmitI()
85 void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm) { in EmitFI() argument
90 imm; in EmitFI()
1190 void Mips64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, in StoreImmediateToFrame() argument
1194 LoadConst32(scratch.AsGpuRegister(), imm); in StoreImmediateToFrame()
1198 void Mips64Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, in StoreImmediateToThread64() argument
1204 LoadConst32(scratch.AsGpuRegister(), imm); in StoreImmediateToThread64()
/art/compiler/utils/arm64/
Dassembler_arm64.h104 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE;
105 void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch)
Dassembler_arm64.cc156 void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm, in StoreImmediateToFrame() argument
160 LoadImmediate(scratch.AsXRegister(), imm); in StoreImmediateToFrame()
165 void Arm64Assembler::StoreImmediateToThread64(ThreadOffset<8> offs, uint32_t imm, in StoreImmediateToThread64() argument
169 LoadImmediate(scratch.AsXRegister(), imm); in StoreImmediateToThread64()
/art/compiler/utils/arm/
Dassembler_thumb2.cc844 uint32_t imm = so.GetImmediate(); in Emit32BitDataProcessing() local
846 uint32_t i = (imm >> 11) & 1; in Emit32BitDataProcessing()
847 uint32_t imm3 = (imm >> 8) & 7U /* 0b111 */; in Emit32BitDataProcessing()
848 uint32_t imm8 = imm & 0xff; in Emit32BitDataProcessing()
860 uint32_t imm = ModifiedImmediate(so.encodingThumb()); in Emit32BitDataProcessing() local
861 if (imm == kInvalidModifiedImmediate) { in Emit32BitDataProcessing()
870 imm; in Emit32BitDataProcessing()
1700 void Thumb2Assembler::ldrex(Register rt, Register rn, uint16_t imm, Condition cond) { in ldrex() argument
1704 CHECK_LT(imm, (1u << 10)); in ldrex()
1710 imm >> 2; in ldrex()
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Dassembler_arm32_test.cc176 for (uint32_t imm = 1; imm < 32; ++imm) { in SetUpHelpers() local
177 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, imm)); in SetUpHelpers()
Dassembler_arm.cc556 void ArmAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, in StoreImmediateToFrame() argument
560 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToFrame()
564 void ArmAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, in StoreImmediateToThread32() argument
568 LoadImmediate(scratch.AsCoreRegister(), imm); in StoreImmediateToThread32()
/art/compiler/dex/quick/arm64/
Dtarget_arm64.cc417 uint64_t imm = DecodeLogicalImmediate(is_wide, operand); in BuildInsnString() local
418 snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm); in BuildInsnString()

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