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Searched refs:info2 (Results 1 – 3 of 3) sorted by relevance

/art/compiler/dex/quick/
Dralloc_util.cc729 RegisterInfo* info2 = GetRegInfo(reg.GetHigh()); in FlushRegWide() local
730 DCHECK(info1 && info2 && info1->IsWide() && info2->IsWide() && in FlushRegWide()
731 (info1->Partner().ExactlyEquals(info2->GetReg())) && in FlushRegWide()
732 (info2->Partner().ExactlyEquals(info1->GetReg()))); in FlushRegWide()
733 if ((info1->IsLive() && info1->IsDirty()) || (info2->IsLive() && info2->IsDirty())) { in FlushRegWide()
734 if (!(info1->IsTemp() && info2->IsTemp())) { in FlushRegWide()
740 info2->SetIsDirty(false); in FlushRegWide()
741 if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) { in FlushRegWide()
742 info1 = info2; in FlushRegWide()
Dmir_to_lir-inl.h132 int info2) { in NewLIR5() argument
137 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info1, info2); in NewLIR5()
Dmir_to_lir.h661 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2);
1172 RegisterInfo* info2 = GetRegInfo(reg2); in IsSameReg() local
1173 return (info1->Master() == info2->Master() && in IsSameReg()
1174 (info1->StorageMask() & info2->StorageMask()) != 0); in IsSameReg()