| /art/compiler/utils/mips64/ |
| D | constants_mips64.h | 45 kFmtShift = 21, enumerator
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| D | assembler_mips64.cc | 77 fmt << kFmtShift | in EmitFR()
88 fmt << kFmtShift | in EmitFI()
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| /art/compiler/utils/mips/ |
| D | constants_mips.h | 69 kFmtShift = 21, enumerator
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| D | assembler_mips.cc | 76 fmt << kFmtShift | in EmitFR()
87 fmt << kFmtShift | in EmitFI()
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| /art/compiler/dex/quick/arm64/ |
| D | assemble_arm64.cc | 122 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
144 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
190 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1,
202 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1,
239 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
488 kFmtRegR, 4, 0, kFmtRegR, 20, 16, kFmtShift, -1, -1,
501 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
629 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
644 kFmtRegR, 9, 5, kFmtRegR, 20, 16, kFmtShift, -1, -1,
815 case kFmtShift: in EncodeLIRs()
[all …]
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| D | arm64_lir.h | 414 kFmtShift, // Register shift, 9-bit at [23..21, 15..10].. enumerator
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| D | utility_arm64.cc | 621 if (kind == kFmtShift) { in OpRegRegShift()
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| /art/compiler/dex/quick/arm/ |
| D | assemble_arm.cc | 577 kFmtShift, -1, -1,
582 kFmtShift, -1, -1,
587 kFmtShift, -1, -1,
591 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
695 kFmtShift, -1, -1,
700 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
704 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
707 kFmtBitBlt, 19, 16, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
713 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
728 kFmtBitBlt, 11, 8, kFmtBitBlt, 3, 0, kFmtShift, -1, -1,
[all …]
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| D | arm_lir.h | 576 kFmtShift, // Shift descriptor, [14..12,7..4]. enumerator
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| D | utility_arm.cc | 405 if (EncodingMap[opcode].field_loc[2].kind == kFmtShift) { in OpRegRegShift()
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