Searched refs:left_op (Results 1 – 9 of 9) sorted by relevance
| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 112 RegStorage left_op = RegStorage::InvalidReg(); // The operands. in GenSelect() local
120 left_op = zero_reg; in GenSelect()
122 left_op = rs_dest; in GenSelect()
132 right_op = left_op; in GenSelect()
135 right_op = left_op; in GenSelect()
138 right_op = left_op; in GenSelect()
165 OpRegRegImm(kOpAdd, t_reg2, left_op, delta); in GenSelect()
178 DCHECK(left_op.Valid() && right_op.Valid()); in GenSelect()
179 NewLIR4(is_wide ? WIDE(opcode) : opcode, rs_dest.GetReg(), left_op.GetReg(), right_op.GetReg(), in GenSelect()
183 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32() argument
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| D | codegen_arm64.h | 181 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
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| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 212 void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32() argument
215 DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); in GenSelectConst32()
216 DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); in GenSelectConst32()
225 const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); in GenSelectConst32()
232 OpRegReg(kOpCmp, left_op, right_op); in GenSelectConst32()
252 OpRegReg(kOpCmp, left_op, right_op); in GenSelectConst32()
261 LIR* cmp_branch = OpCmpBranch(code, left_op, right_op, nullptr); in GenSelectConst32()
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| D | codegen_x86.h | 271 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
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| /art/compiler/dex/quick/mips/ |
| D | int_mips.cc | 280 void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32() argument
287 LIR* ne_branchover = OpCmpBranch(code, left_op, right_op, nullptr); in GenSelectConst32()
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| D | codegen_mips.h | 181 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
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| /art/compiler/dex/quick/arm/ |
| D | codegen_arm.h | 180 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
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| D | int_arm.cc | 217 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32() argument
227 OpRegRegReg(kOpSub, rs_dest, left_op, right_op); in GenSelectConst32()
235 OpRegReg(kOpCmp, left_op, right_op); // Same? in GenSelectConst32()
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| /art/compiler/dex/quick/ |
| D | mir_to_lir.h | 1363 virtual void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
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