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Searched refs:low (Results 1 – 25 of 25) sorted by relevance

/art/compiler/utils/mips/
Dmanaged_register_mips.cc30 Register low = AsRegisterPairLow(); in Overlaps() local
32 return MipsManagedRegister::FromCoreRegister(low).Overlaps(other) || in Overlaps()
38 FRegister low = AsOverlappingDRegisterLow(); in Overlaps() local
41 return (low == other_freg) || (high == other_freg); in Overlaps()
55 int low; in AllocIdLow() local
58 low = (r * 2) + kNumberOfCoreRegIds; // Return an FRegister. in AllocIdLow()
61 low = (r - kNumberOfDRegIds) * 2 + 2; // Return a Register. in AllocIdLow()
62 if (low >= 24) { in AllocIdLow()
64 low = 5; in AllocIdLow()
67 return low; in AllocIdLow()
/art/compiler/utils/arm/
Dmanaged_register_arm.cc29 Register low = AsRegisterPairLow(); in Overlaps() local
31 return ArmManagedRegister::FromCoreRegister(low).Overlaps(other) || in Overlaps()
37 SRegister low = AsOverlappingDRegisterLow(); in Overlaps() local
40 return (low == other_sreg) || (high == other_sreg); in Overlaps()
54 int low; in AllocIdLow() local
57 low = (r * 2) + kNumberOfCoreRegIds; // Return a SRegister. in AllocIdLow()
60 low = (r - kNumberOfDRegIds) * 2; // Return a Register. in AllocIdLow()
61 if (low > 6) { in AllocIdLow()
63 low = 1; in AllocIdLow()
66 return low; in AllocIdLow()
Dassembler_arm.h568 SRegister low = static_cast<SRegister>(sd << 1); variable
569 SRegister high = static_cast<SRegister>(low + 1);
570 LoadSImmediate(low, bit_cast<float, uint32_t>(Low32Bits(int_value)), cond);
572 vmovs(high, low);
/art/compiler/utils/x86/
Dmanaged_register_x86.cc42 Register low; member
48 #define REGISTER_PAIR_ENUMERATION(low, high) { low##_##high, low, high }, argument
68 Register low = AsRegisterPairLow(); in Overlaps() local
70 return X86ManagedRegister::FromCpuRegister(low).Overlaps(other) || in Overlaps()
85 return kRegisterPairs[r].low; in AllocIdLow()
/art/compiler/utils/x86_64/
Dmanaged_register_x86_64.cc41 Register low; member
47 #define REGISTER_PAIR_ENUMERATION(low, high) { low##_##high, low, high }, argument
63 Register low = AsRegisterPairLow().AsRegister(); in Overlaps() local
65 return X86_64ManagedRegister::FromCpuRegister(low).Overlaps(other) || in Overlaps()
80 return kRegisterPairs[r].low; in AllocIdLow()
/art/compiler/utils/arm64/
Dmanaged_register_arm64.cc67 int low = RegNo(); in RegIdLow() local
69 low += kNumberOfXRegIds; in RegIdLow()
71 low += kNumberOfXRegIds + kNumberOfWRegIds + kNumberOfDRegIds; in RegIdLow()
73 return low; in RegIdLow()
/art/compiler/optimizing/
Dlocations.h130 static Location RegisterPairLocation(int low, int high) { in RegisterPairLocation() argument
131 return Location(kRegisterPair, low << 16 | high); in RegisterPairLocation()
134 static Location FpuRegisterPairLocation(int low, int high) { in FpuRegisterPairLocation() argument
135 return Location(kFpuRegisterPair, low << 16 | high); in FpuRegisterPairLocation()
163 int low() const { in low() function
188 return static_cast<T>(low()); in AsRegisterPairLow()
200 return static_cast<T>(low()); in AsFpuRegisterPairLow()
215 return Location::RegisterLocation(low()); in ToLow()
217 return Location::FpuRegisterLocation(low()); in ToLow()
Dcode_generator.cc797 int low = location.low(); in RecordPcInfo() local
799 if (slow_path != nullptr && slow_path->IsFpuRegisterSaved(low)) { in RecordPcInfo()
800 uint32_t offset = slow_path->GetStackOffsetOfFpuRegister(low); in RecordPcInfo()
803 stack_map_stream_.AddDexRegisterEntry(i, DexRegisterLocation::Kind::kInFpuRegister, low); in RecordPcInfo()
817 int low = location.low(); in RecordPcInfo() local
819 if (slow_path != nullptr && slow_path->IsCoreRegisterSaved(low)) { in RecordPcInfo()
820 uint32_t offset = slow_path->GetStackOffsetOfCoreRegister(low); in RecordPcInfo()
823 stack_map_stream_.AddDexRegisterEntry(i, DexRegisterLocation::Kind::kInRegister, low); in RecordPcInfo()
Dlocations.cc77 os << location.low() << ":" << location.high(); in operator <<()
Dcode_generator_x86.cc2161 Immediate low(low_value); in VisitMul() local
2168 __ imull(in1_hi, low); in VisitMul()
2172 __ movl(eax, low); in VisitMul()
2831 Register low = loc.AsRegisterPairLow<Register>(); in GenerateShlLong() local
2835 __ addl(low, low); in GenerateShlLong()
2848 __ movl(high, low); in GenerateShlLong()
2850 __ xorl(low, low); in GenerateShlLong()
2853 __ shld(high, low, Immediate(shift)); in GenerateShlLong()
2854 __ shll(low, Immediate(shift)); in GenerateShlLong()
2870 Register low = loc.AsRegisterPairLow<Register>(); in GenerateShrLong() local
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Dgraph_visualizer.cc146 codegen_.DumpFloatingPointRegister(output_, location.low()); in DumpLocation()
150 codegen_.DumpCoreRegister(output_, location.low()); in DumpLocation()
Dregister_allocator.cc36 static bool IsLowOfUnalignedPairInterval(LiveInterval* low) { in IsLowOfUnalignedPairInterval() argument
37 return GetHighForLowRegister(low->GetRegister()) != low->GetHighInterval()->GetRegister(); in IsLowOfUnalignedPairInterval()
355 current->SetRegister(first.low()); in ProcessInstruction()
367 current->SetRegister(output.low()); in ProcessInstruction()
1188 LiveInterval* low = interval->GetLowInterval()->SplitAt(position); in Split() local
1189 new_interval->SetLowInterval(low); in Split()
1190 low->SetHighInterval(new_interval); in Split()
Dparallel_move_resolver.cc67 return Location::RegisterLocation(location.low()); in LowOf()
69 return Location::FpuRegisterLocation(location.low()); in LowOf()
Dcode_generator_arm.cc39 return ((location.low() & 1) == 0) && (location.low() + 1 == location.high()); in ExpectedPairLayout()
1823 Register low = in.AsRegisterPairLow<Register>(); in VisitTypeConversion() local
1854 __ vmovsr(temp2_s, low); in VisitTypeConversion()
1892 Register low = in.AsRegisterPairLow<Register>(); in VisitTypeConversion() local
1915 __ vmovsr(temp_s, low); in VisitTypeConversion()
2524 Register low = first.AsRegisterPairLow<Register>(); in HandleShift() local
2534 __ Lsr(temp, low, temp); in HandleShift()
2539 __ Lsl(o_h, low, temp, false, PL); in HandleShift()
2541 __ Lsl(o_l, low, o_l); in HandleShift()
2545 __ Lsr(o_l, low, o_h); in HandleShift()
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Dssa_liveness_analysis.h751 void SetLowInterval(LiveInterval* low) { in SetLowInterval() argument
753 high_or_low_interval_ = low; in SetLowInterval()
Dssa_liveness_analysis.cc320 return location.IsPair() ? location.low() : location.reg(); in RegisterOrLowRegister()
Dparallel_move_test.cc40 DumpRegisterForTest(os, location.low()); in DumpLocationForTest()
/art/compiler/dex/
Dreg_storage.h272 static RegStorage MakeRegPair(RegStorage low, RegStorage high) { in MakeRegPair() argument
273 DCHECK(!low.IsPair()); in MakeRegPair()
274 DCHECK(low.Is32Bit()); in MakeRegPair()
277 return RegStorage(k64BitPair, low.GetReg(), high.GetReg()); in MakeRegPair()
Dmir_graph.h903 RegLocation GetSrcWide(MIR* mir, int low) { in GetSrcWide() argument
904 RegLocation res = GetRawSrc(mir, low); in GetSrcWide()
/art/runtime/native/
Dlibcore_util_CharsetUtils.cc221 jchar low = (i + 1 != end) ? string->CharAt(i + 1) : 0; in CharsetUtils_toUtf8Bytes() local
222 if (!U16_IS_SURROGATE_LEAD(high) || !U16_IS_SURROGATE_TRAIL(low)) { in CharsetUtils_toUtf8Bytes()
230 ch = U16_GET_SUPPLEMENTARY(high, low); in CharsetUtils_toUtf8Bytes()
Djava_lang_Class.cc193 size_t low = 0; in FindFieldByName() local
197 while (low < high) { in FindFieldByName()
198 auto mid = (low + high) / 2; in FindFieldByName()
204 low = mid + 1; in FindFieldByName()
/art/runtime/jdwp/
Djdwp_request.cc179 uint64_t low = Read4BE(); in Read8BE() local
180 return (high << 32) | low; in Read8BE()
/art/compiler/dex/quick/arm/
Dcodegen_arm.h325 RegStorage low = reg.GetLow(); in As64BitFloatReg() local
327 DCHECK((low.GetRegNum() % 2 == 0) && (low.GetRegNum() + 1 == high.GetRegNum())); in As64BitFloatReg()
329 return RegStorage::FloatSolo64(low.GetRegNum() / 2); in As64BitFloatReg()
/art/runtime/
Dstack_map.cc75 uint16_t low = region.LoadUnaligned<uint16_t>(offset); in LoadAt() local
77 uint32_t value = (high << 16) + low; in LoadAt()
/art/compiler/dex/quick/mips/
Dtarget_mips.cc203 RegStorage low = ret_reg.GetLow(); in TargetReg() local
204 ret_reg = RegStorage::FloatSolo64(low.GetRegNum()); in TargetReg()