| /art/runtime/arch/arm/ |
| D | memcmp16_arm.S | 33 pld [r1, #0]
36 cmp r0, r1
56 pld [r1, #32]
59 ldrh ip, [r1], #2
78 ldrh ip, [r1], #2
91 eor r0, r3, r1
101 ldr ip, [r1]
107 pld [r1, #64]
109 ldr lr, [r1, #4]!
112 ldreq ip, [r1, #4]!
[all …]
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| D | quick_entrypoints_arm.S | 110 push {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
112 .cfi_rel_offset r1, 0
153 pop {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves
154 .cfi_restore r1
187 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r0, r1 @ save callee saves for throw
195 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r0, r1 // save all registers as basis for long jump context
204 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r1, r2 // save all registers as basis for long jump context
205 mov r1, r9 @ pass Thread::Current
228 RETURN_OR_DELIVER_PENDING_EXCEPTION_REG r1
245 SETUP_REFS_ONLY_CALLEE_SAVE_FRAME r1, r2 @ save callee saves in case of GC
[all …]
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| D | jni_entrypoints_arm.S | 24 push {r0, r1, r2, r3, lr} @ spill regs
27 .cfi_rel_offset r1, 4
38 pop {r0, r1, r2, r3, lr} @ restore regs
41 .cfi_restore r1
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| D | instruction_set_features_assembly_tests.S | 27 mov r1,#1
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| /art/compiler/utils/ |
| D | assembler_thumb_test_expected.cc.inc | 2 " 0: 0008 movs r0, r1\n",
9 " 0: ea4f 0001 mov.w r0, r1\n",
14 " 0: 0008 movs r0, r1\n",
15 " 2: 1888 adds r0, r1, r2\n",
16 " 4: 1c08 adds r0, r1, #0\n",
20 " 0: 0008 movs r0, r1\n",
21 " 2: 43c8 mvns r0, r1\n",
22 " 4: 1888 adds r0, r1, r2\n",
23 " 6: 1a88 subs r0, r1, r2\n",
24 " 8: ea01 0002 and.w r0, r1, r2\n",
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| /art/compiler/driver/ |
| D | compiler_driver.h | 702 static constexpr uint32_t r1 = 15; in operator() local
716 k = (k << r1) | (k >> (32 - r1)); in operator()
737 k1 = (k1 << r1) | (k1 >> (32 - r1)); in operator()
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| /art/runtime/gc/allocator/ |
| D | rosalloc.h | 409 bool operator()(const RosAlloc::Run* r1, const RosAlloc::Run* r2) const { in operator()
410 return r1 == r2; in operator()
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| /art/compiler/dex/quick/x86/ |
| D | x86_lir.h | 125 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1, enumerator
127 rCX = r1,
230 constexpr RegStorage rs_r1(RegStorage::kValid | r1);
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| /art/compiler/dex/quick/arm/ |
| D | arm_lir.h | 116 r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1, enumerator
210 constexpr RegStorage rs_r1(RegStorage::kValid | r1);
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.cc | 736 GpuRegister r1 = loc1.AsRegister<GpuRegister>(); in SwapLocations() local
739 __ Move(r2, r1); in SwapLocations()
740 __ Move(r1, TMP); in SwapLocations()
743 FpuRegister r1 = loc1.AsFpuRegister<FpuRegister>(); in SwapLocations() local
748 __ Dmfc1(AT, r1); in SwapLocations()
749 __ Dmtc1(TMP, r1); in SwapLocations()
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| /art/test/082-inline-execute/src/ |
| D | Main.java | 1024 long r1 = Long.reverse(l1);
1041 return (r1 / i1) + (r2 / i2) + i3 + i4 + i5 + i6 + i7 + i8;
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| /art/runtime/arch/mips/ |
| D | quick_entrypoints_mips.S | 375 move $v0, $zero # clear result registers r0 and r1
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| /art/compiler/jni/ |
| D | jni_cfi_test_expected.inc | 50 // 0x0000000c: str.w r1, [sp, #132]
|