| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 615 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { in GenDivRemLit() argument
623 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); in GenDivRemLit()
1447 static uint32_t GenPairWise(uint32_t reg_mask, int* reg1, int* reg2) { in GenPairWise() argument
1450 int reg = *reg1 + first_bit_set; in GenPairWise()
1458 *reg1 = reg + second_bit_set; in GenPairWise()
1463 *reg1 = reg; in GenPairWise()
1477 int reg1 = -1, reg2 = -1; in SpillCoreRegs() local
1481 reg_mask = GenPairWise(reg_mask, & reg1, & reg2); in SpillCoreRegs()
1483 m2l->NewLIR3(WIDE(kA64Str3rXD), RegStorage::Solo64(reg1).GetReg(), base.GetReg(), offset); in SpillCoreRegs()
1484 m2l->cfi().RelOffset(DwarfCoreReg(reg1), offset << reg_log2_size); in SpillCoreRegs()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_test.h | 122 for (auto reg1 : reg1_registers) { in RepeatTemplatedRRIIC() local
125 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedRRIIC()
147 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c); in RepeatTemplatedRRIIC()
214 for (auto reg1 : reg1_registers) { in RepeatTemplatedRRiiC() local
217 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedRRiiC()
239 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c); in RepeatTemplatedRRiiC()
277 for (auto reg1 : reg1_registers) { in RepeatTemplatedRRC() local
280 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedRRC()
302 (Base::GetAssembler()->*f)(*reg1, *reg2, c); in RepeatTemplatedRRC()
343 for (auto reg1 : reg1_registers) { in RepeatTemplatedRRRC() local
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| D | assembler_arm.h | 784 static int RegisterCompare(const Register* reg1, const Register* reg2) { in RegisterCompare() argument
785 return *reg1 - *reg2; in RegisterCompare()
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| /art/compiler/dex/ |
| D | reg_storage.h | 280 static constexpr bool SameRegType(RegStorage reg1, RegStorage reg2) { in SameRegType() argument
281 return ((reg1.reg_ & kShapeTypeMask) == (reg2.reg_ & kShapeTypeMask)); in SameRegType()
284 static constexpr bool SameRegType(int reg1, int reg2) { in SameRegType() argument
285 return ((reg1 & kShapeTypeMask) == (reg2 & kShapeTypeMask)); in SameRegType()
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| D | type_inference_test.cc | 131 #define DEF_INVOKE2(bb, opcode, reg1, reg2, method_idx) \ argument
132 { bb, opcode, 0u, method_idx, 2, { reg1, reg2 }, 0, { } }
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| /art/compiler/utils/ |
| D | assembler_test.h | 381 for (auto reg1 : reg1_registers) { in RepeatTemplatedRegisters() local
383 (assembler_.get()->*f)(*reg1, *reg2); in RepeatTemplatedRegisters()
386 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedRegisters()
421 for (auto reg1 : reg1_registers) { in RepeatTemplatedRegistersImm() local
425 (assembler_.get()->*f)(*reg1, *reg2, new_imm); in RepeatTemplatedRegistersImm()
428 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedRegistersImm()
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| /art/compiler/dex/quick/mips/ |
| D | int_mips.cc | 303 RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, in GenDivRem() argument
308 NewLIR3(is_div ? kMipsR6Div : kMipsR6Mod, rl_result.reg.GetReg(), reg1.GetReg(), reg2.GetReg()); in GenDivRem()
310 NewLIR2(kMipsR2Div, reg1.GetReg(), reg2.GetReg()); in GenDivRem()
316 RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { in GenDivRemLit() argument
325 RegLocation rl_result = GenDivRem(rl_dest, reg1, t_reg, is_div); in GenDivRemLit()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.cc | 1214 void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) { in cmpl() argument
1216 EmitOptionalRex32(reg0, reg1); in cmpl()
1218 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpl()
1245 void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) { in cmpq() argument
1247 EmitRex64(reg0, reg1); in cmpq()
1249 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpq()
1293 void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) { in testl() argument
1295 EmitOptionalRex32(reg1, reg2); in testl()
1297 EmitRegisterOperand(reg1.LowBits(), reg2.LowBits()); in testl()
1335 void X86_64Assembler::testq(CpuRegister reg1, CpuRegister reg2) { in testq() argument
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| D | assembler_x86_64.h | 478 void cmpl(CpuRegister reg0, CpuRegister reg1);
483 void cmpq(CpuRegister reg0, CpuRegister reg1);
488 void testl(CpuRegister reg1, CpuRegister reg2);
492 void testq(CpuRegister reg1, CpuRegister reg2);
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| /art/compiler/utils/x86/ |
| D | assembler_x86.h | 368 void cmpl(Register reg0, Register reg1);
374 void testl(Register reg1, Register reg2);
376 void testl(Register reg1, const Address& address);
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| D | assembler_x86.cc | 970 void X86Assembler::cmpl(Register reg0, Register reg1) { in cmpl() argument
973 EmitOperand(reg0, Operand(reg1)); in cmpl()
1011 void X86Assembler::testl(Register reg1, Register reg2) { in testl() argument
1014 EmitRegisterOperand(reg1, reg2); in testl()
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| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 729 RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) { in GenDivRemLit() argument
737 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div); in GenDivRemLit()
743 RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, in GenDivRem() argument
748 OpRegRegReg(kOpDiv, rl_result.reg, reg1, reg2); in GenDivRem()
756 OpRegRegReg(kOpDiv, temp, reg1, reg2); in GenDivRem()
758 OpRegRegReg(kOpSub, rl_result.reg, reg1, temp); in GenDivRem()
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| /art/compiler/dex/quick/ |
| D | mir_to_lir.h | 1170 bool IsSameReg(RegStorage reg1, RegStorage reg2) { in IsSameReg() argument
1171 RegisterInfo* info1 = GetRegInfo(reg1); in IsSameReg()
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| /art/compiler/dex/quick/x86/ |
| D | codegen_x86.h | 848 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
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| D | int_x86.cc | 1091 void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { in OpLea() argument
1092 NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); in OpLea()
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| /art/compiler/optimizing/ |
| D | code_generator_arm.cc | 2362 Register reg1 = first.AsRegister<Register>(); in VisitRem() local
2369 __ sdiv(temp, reg1, reg2); in VisitRem()
2371 __ sub(out.AsRegister<Register>(), reg1, ShifterOperand(temp)); in VisitRem()
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