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Searched refs:reg_w (Results 1 – 3 of 3) sorted by relevance

/art/compiler/utils/arm64/
Dassembler_arm64.cc99 ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset)); in StoreWToOffset()
102 ___ Strh(reg_w(source), MEM_OP(reg_x(base), offset)); in StoreWToOffset()
105 ___ Str(reg_w(source), MEM_OP(reg_x(base), offset)); in StoreWToOffset()
222 ___ Ldrsb(reg_w(dest), MEM_OP(reg_x(base), offset)); in LoadWFromOffset()
225 ___ Ldrsh(reg_w(dest), MEM_OP(reg_x(base), offset)); in LoadWFromOffset()
228 ___ Ldrb(reg_w(dest), MEM_OP(reg_x(base), offset)); in LoadWFromOffset()
231 ___ Ldrh(reg_w(dest), MEM_OP(reg_x(base), offset)); in LoadWFromOffset()
234 ___ Ldr(reg_w(dest), MEM_OP(reg_x(base), offset)); in LoadWFromOffset()
265 ___ Ldr(reg_w(dest.AsWRegister()), MEM_OP(reg_x(base), offset)); in Load()
269 ___ Ldr(reg_w(dest.AsOverlappingWRegister()), MEM_OP(reg_x(base), offset)); in Load()
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Dmanaged_register_arm64_test.cc635 EXPECT_TRUE(vixl::w0.Is(Arm64Assembler::reg_w(W0))); in TEST()
636 EXPECT_TRUE(vixl::w1.Is(Arm64Assembler::reg_w(W1))); in TEST()
637 EXPECT_TRUE(vixl::w2.Is(Arm64Assembler::reg_w(W2))); in TEST()
638 EXPECT_TRUE(vixl::w3.Is(Arm64Assembler::reg_w(W3))); in TEST()
639 EXPECT_TRUE(vixl::w4.Is(Arm64Assembler::reg_w(W4))); in TEST()
640 EXPECT_TRUE(vixl::w5.Is(Arm64Assembler::reg_w(W5))); in TEST()
641 EXPECT_TRUE(vixl::w6.Is(Arm64Assembler::reg_w(W6))); in TEST()
642 EXPECT_TRUE(vixl::w7.Is(Arm64Assembler::reg_w(W7))); in TEST()
643 EXPECT_TRUE(vixl::w8.Is(Arm64Assembler::reg_w(W8))); in TEST()
644 EXPECT_TRUE(vixl::w9.Is(Arm64Assembler::reg_w(W9))); in TEST()
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Dassembler_arm64.h195 static vixl::Register reg_w(int code) { in reg_w() function