Searched refs:rl_false (Results 1 – 3 of 3) sorted by relevance
| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 296 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]; in GenSelect() local
298 rl_false = LoadValue(rl_false, result_reg_class); in GenSelect()
304 OpRegCopy(rl_result.reg, rl_false.reg); in GenSelect()
305 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { // False case in place? in GenSelect()
311 OpRegCopy(rl_result.reg, rl_false.reg); in GenSelect()
|
| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 208 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]; in GenSelect() local
212 rl_false = LoadValue(rl_false, result_reg_class); in GenSelect()
218 rl_true.reg.GetReg(), rl_false.reg.GetReg(), ArmConditionEncoding(mir->meta.ccode)); in GenSelect()
|
| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 352 RegLocation rl_false = mir_graph_->GetSrc(mir, 2); in GenSelect() local
354 rl_false = LoadValue(rl_false, result_reg_class); in GenSelect()
376 OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); in GenSelect()
377 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { in GenSelect()
380 OpRegCopy(rl_result.reg, rl_false.reg); in GenSelect()
|