Searched refs:rl_src_offset (Results 1 – 4 of 4) sorted by relevance
| /art/compiler/dex/quick/ |
| D | gen_invoke.cc | 1449 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedUnsafeGet() local
1450 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedUnsafeGet()
1454 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedUnsafeGet()
1494 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedUnsafePut() local
1495 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedUnsafePut()
1501 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedUnsafePut()
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| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 1113 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedCas() local
1115 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedCas()
1131 RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); in GenInlinedCas()
1153 const bool off_in_di = IsInReg(this, rl_src_offset, rs_rDI); in GenInlinedCas()
1154 const bool off_in_si = IsInReg(this, rl_src_offset, rs_rSI); in GenInlinedCas()
1192 LoadWordDisp(rs_rSP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); in GenInlinedCas()
1243 rl_offset = LoadValueWide(rl_src_offset, kCoreReg); in GenInlinedCas()
1245 rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedCas()
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| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 834 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedCas() local
835 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedCas()
900 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedCas()
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| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 744 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedCas() local
753 RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); in GenInlinedCas()
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