| /art/compiler/dex/quick/x86/ |
| D | target_x86.cc | 1537 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenConst128() local
1538 Clobber(rs_dest); in GenConst128()
1541 int reg = rs_dest.GetReg(); in GenConst128()
1592 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenMoveVector() local
1593 Clobber(rs_dest); in GenMoveVector()
1595 NewLIR2(kX86MovdqaRR, rs_dest.GetReg(), rs_src.GetReg()); in GenMoveVector()
2237 void X86Mir2Lir::LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, in LoadVectorRegister() argument
2241 NewLIR2(kX86MovdxrRR, rs_dest.GetReg(), rs_src.GetLowReg()); in LoadVectorRegister()
2244 NewLIR2(kX86PunpckldqRR, rs_dest.GetReg(), r_tmp.GetReg()); in LoadVectorRegister()
2247 NewLIR2(op_mov, rs_dest.GetReg(), rs_src.GetReg()); in LoadVectorRegister()
[all …]
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| D | int_x86.cc | 213 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
215 DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); in GenSelectConst32()
216 DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); in GenSelectConst32()
221 LoadConstantNoClobber(rs_dest, true_val); in GenSelectConst32()
225 const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); in GenSelectConst32()
228 if (zero_one_case && IsByteRegister(rs_dest)) { in GenSelectConst32()
230 LoadConstantNoClobber(rs_dest, 0); in GenSelectConst32()
234 NewLIR2(kX86Set8R, rs_dest.GetReg(), in GenSelectConst32()
237 NewLIR2(rs_dest.Is64Bit() ? kX86Movzx8qRR : kX86Movzx8RR, rs_dest.GetReg(), rs_dest.GetReg()); in GenSelectConst32()
249 LoadConstantNoClobber(rs_dest, false_val); in GenSelectConst32()
[all …]
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| D | codegen_x86.h | 272 int32_t true_val, int32_t false_val, RegStorage rs_dest,
508 virtual void LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, OpSize opsize,
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| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 100 RegStorage rs_dest, int result_reg_class) { in GenSelect() argument
115 bool is_wide = rs_dest.Is64Bit(); in GenSelect()
122 left_op = rs_dest; in GenSelect()
123 LoadConstantNoClobber(rs_dest, true_val); in GenSelect()
142 right_op = rs_dest; in GenSelect()
143 LoadConstantNoClobber(rs_dest, false_val); in GenSelect()
179 NewLIR4(is_wide ? WIDE(opcode) : opcode, rs_dest.GetReg(), left_op.GetReg(), right_op.GetReg(), in GenSelect()
184 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
186 DCHECK(rs_dest.Valid()); in GenSelectConst32()
188 GenSelect(true_val, false_val, code, rs_dest, dest_reg_class); in GenSelectConst32()
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| D | codegen_arm64.h | 182 int32_t true_val, int32_t false_val, RegStorage rs_dest,
392 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest,
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| /art/compiler/dex/quick/mips/ |
| D | int_mips.cc | 281 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
286 LoadConstant(rs_dest, true_val); in GenSelectConst32()
288 LoadConstant(rs_dest, false_val); in GenSelectConst32()
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| D | codegen_mips.h | 182 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 218 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
227 OpRegRegReg(kOpSub, rs_dest, left_op, right_op); in GenSelectConst32()
230 LoadConstant(rs_dest, code == kCondEq ? false_val : true_val); in GenSelectConst32()
237 LoadConstant(rs_dest, true_val); // .eq case - load true in GenSelectConst32()
238 LoadConstant(rs_dest, false_val); // .eq case - load true in GenSelectConst32()
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| D | codegen_arm.h | 181 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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| /art/compiler/dex/quick/ |
| D | mir_to_lir.h | 1364 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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