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Searched refs:s_reg_low (Results 1 – 19 of 19) sorted by relevance

/art/compiler/dex/quick/
Dgen_loadstore.cc64 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, op_size, kNotVolatile); in LoadValueDirect()
94 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64, kNotVolatile); in LoadValueDirectWide()
127 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); in LoadValue()
143 (rl_dest.s_reg_low != live_sreg_)); in StoreValue()
144 live_sreg_ = rl_dest.s_reg_low; in StoreValue()
176 if (IsDirty(rl_dest.reg) && LiveOut(rl_dest.s_reg_low)) { in StoreValue()
180 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, kNotVolatile); in StoreValue()
182 Store32Disp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg); in StoreValue()
211 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); in LoadValueWide()
212 DCHECK_NE(GetSRegHi(rl_src.s_reg_low), INVALID_SREG); in LoadValueWide()
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Dralloc_util.cc699 NullifyRange(rl.reg, rl.s_reg_low); in ResetDefLoc()
709 NullifyRange(rs, rl.s_reg_low); in ResetDefLocWide()
808 int s_reg = loc.s_reg_low; in MarkLive()
997 RegStorage reg = AllocLiveReg(loc.s_reg_low, loc.ref ? kRefReg : kAnyReg, false); in UpdateLoc()
1022 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true); in UpdateLocWide()
1080 DCHECK_NE(loc.s_reg_low, INVALID_SREG); in EvalLocWide()
1081 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); in EvalLocWide()
1120 DCHECK_NE(loc.s_reg_low, INVALID_SREG); in EvalLoc()
1266 core_counts[SRegToPMap(mir_graph_->GetMethodLoc().s_reg_low)].count += weight; in AnalyzeMIR()
1270 core_counts[SRegToPMap(pc_rel_temp_->s_reg_low)].count += weight; in AnalyzeMIR()
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Dgen_invoke.cc706 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); in GenDalvikArgsFlushPromoted()
713 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile); in GenDalvikArgsFlushPromoted()
715 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k32, in GenDalvikArgsFlushPromoted()
741 int start_offset = SRegOffset(info->args[first].s_reg_low); in GenDalvikArgsBulkCopy()
855 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_arg.s_reg_low + 1), reg, k32, in GenDalvikArgs()
859 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_arg.s_reg_low), reg, k32, kNotVolatile); in GenDalvikArgs()
1172 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedReverseBytes()
1208 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedAbsInt()
1226 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedAbsLong()
1307 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedFloatCvt()
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Dcodegen_util.cc69 rl_src.s_reg_low--; in IsInexpensiveConstant()
1248 …return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) … in PartiallyIntersects()
1254 …return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) … in Intersects()
1344 if (info->IsLive() && (info->SReg() == loc.s_reg_low)) { in NarrowRegLoc()
1346 info_new->MarkLive(loc.s_reg_low); in NarrowRegLoc()
Dgen_common.cc569 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile); in GenFilledNewArray()
571 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); in GenFilledNewArray()
603 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); in GenFilledNewArray()
/art/compiler/dex/
Dvreg_analysis.cc37 table[i].s_reg_low); in DumpRegLocTable()
53 loc[i].s_reg_low = i; in InitRegLocations()
70 int orig_sreg = reg_location_[i].s_reg_low; in RemapRegLocations()
72 reg_location_[i].s_reg_low = SRegToVReg(orig_sreg); in RemapRegLocations()
Dreg_location.h54 int16_t s_reg_low; // SSA name for low Dalvik word. member
Dmir_graph.h196 int32_t s_reg_low; // SSA name for low Dalvik word. member
807 int64_t ConstantValueWide(int32_t s_reg_low, int32_t s_reg_high) const { in ConstantValueWide() argument
808 DCHECK(IsConst(s_reg_low)); in ConstantValueWide()
811 Low32Bits(static_cast<int64_t>(constant_values_[s_reg_low])); in ConstantValueWide()
Dmir_optimization.cc371 compiler_temp->s_reg_low = AddNewSReg(compiler_temp->v_reg); in GetNewCompilerTemp()
375 << compiler_temp->v_reg << " and s" << compiler_temp->s_reg_low << " has been created."; in GetNewCompilerTemp()
384 int ssa_reg_low = compiler_temp->s_reg_low; in GetNewCompilerTemp()
396 reg_location_[ssa_reg_high].s_reg_low = ssa_reg_low; in GetNewCompilerTemp()
406 int ssa_reg_low = compiler_temp->s_reg_low; in GetNewCompilerTemp()
408 reg_location_[ssa_reg_low].s_reg_low = ssa_reg_low; in GetNewCompilerTemp()
Dmir_dataflow.cc1380 method_sreg_ = method_temp->s_reg_low; in CompilerInitializeSSAConversion()
/art/compiler/dex/quick/x86/
Dfp_x86.cc143 int src_v_reg_offset = SRegOffset(rl_src.s_reg_low); in GenLongToFP()
144 int dest_v_reg_offset = SRegOffset(rl_dest.s_reg_low); in GenLongToFP()
235 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
256 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
294 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
320 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
363 int src1_v_reg_offset = SRegOffset(rl_src1.s_reg_low); in GenRemFP()
364 int src2_v_reg_offset = SRegOffset(rl_src2.s_reg_low); in GenRemFP()
365 int dest_v_reg_offset = SRegOffset(rl_dest.s_reg_low); in GenRemFP()
479 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
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Dint_x86.cc871 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedMinMax()
907 if (mir_graph_->SRegToVReg(rl_src1.s_reg_low) == in GenInlinedMinMax()
908 mir_graph_->SRegToVReg(rl_src2.s_reg_low)) { in GenInlinedMinMax()
989 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedMinMax()
1033 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedPeek()
1185 LoadWordDisp(rs_rSP, SRegOffset(rl_src_obj.s_reg_low) + push_offset, rs_obj); in GenInlinedCas()
1192 LoadWordDisp(rs_rSP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); in GenInlinedCas()
1305 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedReverseBits()
1773 int displacement = SRegOffset(rl_src1.s_reg_low); in GenMulLongConst()
1781 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); in GenMulLongConst()
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Dutility_x86.cc400 int displacement = SRegOffset(rl_dest.s_reg_low); in OpMemReg()
429 int displacement = SRegOffset(rl_value.s_reg_low); in OpRegMem()
1022 core_counts[SRegToPMap(pc_rel_temp_->s_reg_low)].count += weight; in AnalyzeMIR()
1135 int p_map_idx = SRegToPMap(pc_rel_temp_->s_reg_low); in CountRefs()
1154 pc_rel_base_reg_ = mir_graph_->reg_location_[pc_rel_temp_->s_reg_low].reg; in DoPromotion()
Dtarget_x86.cc906 int displacement = SRegOffset(rl_dest.s_reg_low); in GenConstWide()
935 << ", s_reg: " << loc.s_reg_low in DumpRegLocation()
1360 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); in GenInlinedIndexOf()
2228 int displacement = SRegOffset(rl_result.s_reg_low); in GenReduceVector()
2530 int current_src_offset = SRegOffset(info->args[first].s_reg_low); in GenDalvikArgsBulkCopy()
/art/compiler/dex/quick/arm/
Dint_arm.cc871 ClobberSReg(rl_src_expected.s_reg_low); in GenInlinedCas()
872 ClobberSReg(GetSRegHi(rl_src_expected.s_reg_low)); in GenInlinedCas()
877 ClobberSReg(rl_src_new_value.s_reg_low); in GenInlinedCas()
878 ClobberSReg(GetSRegHi(rl_src_new_value.s_reg_low)); in GenInlinedCas()
906 ClobberSReg(rl_object.s_reg_low); in GenInlinedCas()
908 ClobberSReg(rl_offset.s_reg_low); in GenInlinedCas()
1281 if ((rl_dest.s_reg_low != rl_src1.s_reg_low && rl_dest.s_reg_low != rl_src2.s_reg_low) && in GenMulLong()
1289 if ((rl_src1.s_reg_low == rl_src2.s_reg_low) || src1_promoted || src2_promoted) { in GenMulLong()
Dfp_arm.cc326 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
334 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
Dutility_arm.cc1279 int p_map_idx = SRegToPMap(pc_rel_temp_->s_reg_low); in CountRefs()
1298 dex_cache_arrays_base_reg_ = mir_graph_->reg_location_[pc_rel_temp_->s_reg_low].reg; in DoPromotion()
/art/compiler/dex/quick/arm64/
Dfp_arm64.cc309 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
317 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
Dint_arm64.cc774 ClobberSReg(rl_object.s_reg_low); in GenInlinedCas()
776 ClobberSReg(rl_offset.s_reg_low); in GenInlinedCas()