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Searched refs:temp_reg (Results 1 – 10 of 10) sorted by relevance

/art/compiler/dex/quick/x86/
Dfp_x86.cc237 RegStorage temp_reg = AllocTempSingle(); in GenConversion() local
240 NewLIR2(kX86Cvtsi2ssRR, temp_reg.GetReg(), rl_result.reg.GetReg()); in GenConversion()
241 NewLIR2(kX86ComissRR, rl_src.reg.GetReg(), temp_reg.GetReg()); in GenConversion()
258 RegStorage temp_reg = AllocTempDouble(); in GenConversion() local
261 NewLIR2(kX86Cvtsi2sdRR, temp_reg.GetReg(), rl_result.reg.GetReg()); in GenConversion()
262 NewLIR2(kX86ComisdRR, rl_src.reg.GetReg(), temp_reg.GetReg()); in GenConversion()
296 RegStorage temp_reg = AllocTempSingle(); in GenConversion() local
300 NewLIR2(kX86Cvtsqi2ssRR, temp_reg.GetReg(), rl_result.reg.GetReg()); in GenConversion()
301 NewLIR2(kX86ComissRR, rl_src.reg.GetReg(), temp_reg.GetReg()); in GenConversion()
322 RegStorage temp_reg = AllocTempDouble(); in GenConversion() local
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Dint_x86.cc43 RegStorage temp_reg = AllocTemp(); in GenCmpLong() local
46 NewLIR2(kX86Set8R, temp_reg.GetReg(), kX86CondL); // temp = (src1 >= src2) ? 0 : 1 in GenCmpLong()
47 NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg()); in GenCmpLong()
51 FreeTemp(temp_reg); in GenCmpLong()
179 RegStorage temp_reg = AllocTempDouble(); in OpRegCopyWide() local
180 NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); in OpRegCopyWide()
181 NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); in OpRegCopyWide()
182 NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); in OpRegCopyWide()
194 RegStorage temp_reg = AllocTemp(); in OpRegCopyWide() local
195 OpRegCopy(temp_reg, r_dest.GetHigh()); in OpRegCopyWide()
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Dutility_x86.cc945 LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch() argument
947 UNUSED(temp_reg); // Comparison performed directly with memory. in OpCmpMemImmBranch()
Dcodegen_x86.h814 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
/art/runtime/arch/x86/
Dquick_entrypoints_x86.S25 MACRO2(SETUP_SAVE_ALL_CALLEE_SAVE_FRAME, got_reg, temp_reg)
33 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg, 0)), REG_VAR(temp_reg, 1)
34 movl (REG_VAR(temp_reg, 1)), REG_VAR(temp_reg, 1)
36 pushl RUNTIME_SAVE_ALL_CALLEE_SAVE_FRAME_OFFSET(REG_VAR(temp_reg, 1))
51 MACRO2(SETUP_REFS_ONLY_CALLEE_SAVE_FRAME, got_reg, temp_reg)
59 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg, 0)), REG_VAR(temp_reg, 1)
60 movl (REG_VAR(temp_reg, 1)), REG_VAR(temp_reg, 1)
62 pushl RUNTIME_REFS_ONLY_CALLEE_SAVE_FRAME_OFFSET(REG_VAR(temp_reg, 1))
86 MACRO2(SETUP_REFS_AND_ARGS_CALLEE_SAVE_FRAME, got_reg, temp_reg)
104 movl SYMBOL(_ZN3art7Runtime9instance_E)@GOT(REG_VAR(got_reg, 0)), REG_VAR(temp_reg, 1)
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/art/compiler/dex/quick/arm64/
Dint_arm64.cc300 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, in OpCmpMemImmBranch() argument
306 if (temp_reg.Is64Bit()) { in OpCmpMemImmBranch()
307 temp_reg = As32BitReg(temp_reg); in OpCmpMemImmBranch()
309 Load32Disp(base_reg, offset, temp_reg); in OpCmpMemImmBranch()
310 LIR* branch = OpCmpImmBranch(cond, temp_reg, check_value, target); in OpCmpMemImmBranch()
Dcodegen_arm64.h85 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
/art/compiler/optimizing/
Dcode_generator_x86.cc4035 Register temp_reg = static_cast<Register>(ensure_scratch.GetRegister()); in MoveMemoryToMemory32() local
4037 __ movl(temp_reg, Address(ESP, src + stack_offset)); in MoveMemoryToMemory32()
4038 __ movl(Address(ESP, dst + stack_offset), temp_reg); in MoveMemoryToMemory32()
4044 Register temp_reg = static_cast<Register>(ensure_scratch.GetRegister()); in MoveMemoryToMemory64() local
4046 __ movl(temp_reg, Address(ESP, src + stack_offset)); in MoveMemoryToMemory64()
4047 __ movl(Address(ESP, dst + stack_offset), temp_reg); in MoveMemoryToMemory64()
4048 __ movl(temp_reg, Address(ESP, src + stack_offset + kX86WordSize)); in MoveMemoryToMemory64()
4049 __ movl(Address(ESP, dst + stack_offset + kX86WordSize), temp_reg); in MoveMemoryToMemory64()
4181 Register temp_reg = static_cast<Register>(ensure_scratch.GetRegister()); in Exchange32() local
4183 __ movl(temp_reg, Address(ESP, mem + stack_offset)); in Exchange32()
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/art/compiler/dex/quick/
Dcodegen_util.cc1257 LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch() argument
1260 LIR* inst = Load32Disp(base_reg, offset, temp_reg); in OpCmpMemImmBranch()
1264 LIR* branch = OpCmpImmBranch(cond, temp_reg, check_value, target); in OpCmpMemImmBranch()
Dmir_to_lir.h1136 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,