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/art/compiler/dex/
Dmir_dataflow.cc929 int type_size = d_insn.vC >> 16; in HandleExtended()
960 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC); in HandleExtended()
968 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC); in HandleExtended()
969 HandleLiveInUse(use_v, def_v, live_in_v, d_insn.vC + 1); in HandleExtended()
1016 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC); in FindLocalLiveIn()
1018 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+1); in FindLocalLiveIn()
1029 HandleLiveInUse(use_v, def_v, live_in_v, d_insn->vC+i); in FindLocalLiveIn()
1113 HandleSSAUse(mir->ssa_rep->uses, d_insn->vC+i, i); in DataFlowSSAFormat3RC()
1121 int type_size = d_insn.vC >> 16; in DataFlowSSAFormatExtended()
1162 HandleSSAUse(mir->ssa_rep->uses, d_insn.vC, 1); in DataFlowSSAFormatExtended()
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Dmir_graph.cc175 decoded_instruction->vC = inst->HasVRegC() ? inst->VRegC() : 0; in ParseInsn()
473 target += insn->dalvikInsn.vC; in ProcessCanBranch()
852 int first_reg_in_range = insn->dalvikInsn.vC; in InlineMethod()
1363 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir); in DisassembleExtendedInstr()
1367 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir); in DisassembleExtendedInstr()
1371 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir); in DisassembleExtendedInstr()
1375 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir); in DisassembleExtendedInstr()
1379 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir); in DisassembleExtendedInstr()
1383 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir); in DisassembleExtendedInstr()
1387 FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir); in DisassembleExtendedInstr()
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Dmir_optimization_test.cc58 uint32_t vC; member
88 #define DEF_AGET_APUT(bb, opcode, vA, vB, vC) \ argument
89 { bb, opcode, 0u, vA, vB, vC }
90 #define DEF_INVOKE(bb, opcode, vC, method_info) \ argument
91 { bb, opcode, method_info, 0u, 0u, vC }
308 mir->dalvikInsn.vC = def->vC; in DoPrepareMIRs()
Dmir_optimization.cc522 IsInstructionIfCc(opcode) ? mir->dalvikInsn.vC : mir->dalvikInsn.vB; in BasicBlockOpt()
589 mir_next->dalvikInsn.vB = mir->dalvikInsn.vC; in BasicBlockOpt()
666 mir->dalvikInsn.vC = if_false->dalvikInsn.vB; in BasicBlockOpt()
1018 src_vreg = mir->dalvikInsn.vC; in EliminateNullChecks()
1681 uint32_t orig_this_reg = is_range ? mir->dalvikInsn.vC : mir->dalvikInsn.arg[0]; in StringChange()
1691 mir->dalvikInsn.vC++; in StringChange()
1925 add_mir->dalvikInsn.vC = SRegToVReg(add_mir->ssa_rep->uses[2]); in CombineMultiplyAdd()
1928 add_mir->dalvikInsn.vC = SRegToVReg(add_mir->ssa_rep->uses[1]); in CombineMultiplyAdd()
Dmir_graph.h260 uint32_t vC; member
264 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) { in DecodedInstruction()
Dglobal_value_numbering_test.cc2361 mirs_[0].dalvikInsn.vC = 1234; // type for instance-of in TEST_F()
2362 mirs_[1].dalvikInsn.vC = 1234; // type for instance-of in TEST_F()
2412 mirs_[0].dalvikInsn.vC = 1234; // type for instance-of in TEST_F()
2413 mirs_[1].dalvikInsn.vC = 1234; // type for instance-of in TEST_F()
Dgvn_dead_code_elimination_test.cc316 mir->dalvikInsn.vC = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_C_WIDE) != 0); in DoPrepareMIRs()
853 EXPECT_EQ(1u, mirs_[2].dalvikInsn.vC); in TEST_F()
891 EXPECT_EQ(1u, mirs_[2].dalvikInsn.vC); in TEST_F()
927 EXPECT_EQ(0u, mirs_[1].dalvikInsn.vC); in TEST_F()
Dmir_analysis.cc1232 field_idx = mir->dalvikInsn.vC; in DoCacheFieldLoweringInfo()
Dgvn_dead_code_elimination.cc515 mir->dalvikInsn.vC = mir->dalvikInsn.vB; in ChangeBinOp2AddrToPlainBinOp()
1326 if (mir->dalvikInsn.vC == 0) { // Explicit division by 0? in RecordMIR()
Dlocal_value_numbering.cc1608 uint16_t type = mir->dalvikInsn.vC; in GetValueNumber()
1909 uint16_t operand2 = gvn_->LookupValue(Instruction::CONST, mir->dalvikInsn.vC, 0, 0); in GetValueNumber()
Dtype_inference.cc799 sregs_[defs[0]] = Type::DexType(cu_->dex_file, mir->dalvikInsn.vC).AsNonNull(); in InitializeSRegs()
Dtype_inference_test.cc425 mir->dalvikInsn.vC = dex_file_builder_.GetTypeIdx(type_defs_[def->metadata].descriptor); in DoPrepareMIRs()
/art/compiler/dex/quick/x86/
Dtarget_x86.cc1591 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenMoveVector()
1706 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenMultiplyVector()
1707 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenMultiplyVector()
1740 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenAddVector()
1741 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenAddVector()
1775 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenSubtractVector()
1776 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSubtractVector()
1854 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenShiftLeftVector()
1855 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenShiftLeftVector()
1883 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenSignedShiftRightVector()
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Dquick_assemble_x86_test.cc208 mir->dalvikInsn.vC = (vector_type << 16) | vector_size; // Type size. in TestVectorFn()
Dutility_x86.cc1001 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in AnalyzeMIR()
Dint_x86.cc288 int false_val = mir->dalvikInsn.vC; in GenSelect()
/art/compiler/dex/quick/
Dmir_to_lir.cc483 const uint32_t vC = mir->dalvikInsn.vC; in CompileDalvikInstruction() local
620 GenInstanceof(vC, rl_dest, rl_src[0]); in CompileDalvikInstruction()
666 GenNewArray(vC, rl_dest, rl_src[0]); in CompileDalvikInstruction()
1126 GenArithOpIntLit(opcode, rl_dest, rl_src[0], vC); in CompileDalvikInstruction()
Ddex_file_method_inliner.cc124 return invoke->dalvikInsn.vC + arg; // Range invoke. in GetInvokeReg()
693 invoke->dalvikInsn.vA = invoke->dalvikInsn.vC; in GenInline()
Dralloc_util.cc1149 (opcode == Instruction::CHECK_CAST) ? mir->dalvikInsn.vB : mir->dalvikInsn.vC; in AnalyzeMIR()
/art/runtime/verifier/
Dmethod_verifier.h451 bool CheckVarArgRangeRegs(uint32_t vA, uint32_t vC);
Dmethod_verifier.cc1209 bool MethodVerifier::CheckVarArgRangeRegs(uint32_t vA, uint32_t vC) { in CheckVarArgRangeRegs() argument
1213 if (vA + vC > registers_size) { in CheckVarArgRangeRegs()
1214 Fail(VERIFY_ERROR_BAD_CLASS_HARD) << "invalid reg index " << vA << "+" << vC in CheckVarArgRangeRegs()
/art/compiler/dex/quick/arm/
Dint_arm.cc255 int false_val = mir->dalvikInsn.vC; in GenSelect()
/art/compiler/dex/quick/arm64/
Dint_arm64.cc203 GenSelect(mir->dalvikInsn.vB, mir->dalvikInsn.vC, mir->meta.ccode, rl_result.reg, in GenSelect()