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Searched refs:RES (Results 1 – 25 of 52) sorted by relevance

123

/external/eigen/blas/fortran/
Dcomplexdots.f4 COMPLEX RES local
7 CALL CDOTCW(N,CX,INCX,CY,INCY,RES)
8 CDOTC = RES
15 COMPLEX RES local
18 CALL CDOTUW(N,CX,INCX,CY,INCY,RES)
19 CDOTU = RES
26 DOUBLE COMPLEX RES local
29 CALL ZDOTCW(N,CX,INCX,CY,INCY,RES)
30 ZDOTC = RES
37 DOUBLE COMPLEX RES local
[all …]
/external/llvm/test/CodeGen/Mips/msa/
Delm_copy.ll31 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_b_RES)
32 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_b_RES)
33 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
54 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_h_RES)
55 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_h_RES)
56 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
77 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_w_RES)
78 ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_s_w_RES)
79 ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]])
103 ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_s_d_RES)
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dlogopm.ll42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
43 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
64 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
87 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
88 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
113 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
114 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
133 ; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1
134 ; CHECK: sb $[[RES]], 0($[[UB_ADDR]])
[all …]
/external/selinux/scripts/
DLindent3 RES=`indent --version`
4 V1=`echo $RES | cut -d' ' -f3 | cut -d'.' -f1`
5 V2=`echo $RES | cut -d' ' -f3 | cut -d'.' -f2`
6 V3=`echo $RES | cut -d' ' -f3 | cut -d'.' -f3`
/external/llvm/test/CodeGen/ARM/
Dvector-promotion.ll128 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = udiv i32 [[EXTRACT]], 7
131 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
133 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
147 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = urem i32 [[EXTRACT]], 7
150 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
152 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
166 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sdiv i32 [[EXTRACT]], 7
169 ; IR-STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[DIV]], i32 1
171 ; IR-BOTH-NEXT: store i32 [[RES]], i32* %dest
185 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7
[all …]
Dadv-copy-opt.ll25 ; NOOPT-NEXT: vmov.32 [[RES:d[0-9]+]][0], [[RES_LOW]]
26 ; NOOPT-NEXT: vmov.32 [[RES]][1], [[RES_HIGH]]
27 ; NOOPT-NEXT: vmov r0, r1, [[RES]]
/external/llvm/test/CodeGen/R600/
Dfma.ll13 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}},
14 ; EG: FMA {{\*? *}}[[RES]]
29 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].[[CHLO:[XYZW]]][[CHHI:[XYZW]]], {{T[0-9]\.[XYZW]}},
30 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHLO]]
31 ; EG-DAG: FMA {{\*? *}}[[RES]].[[CHHI]]
48 ; EG: MEM_RAT_{{.*}} STORE_{{.*}} [[RES:T[0-9]]].{{[XYZW][XYZW][XYZW][XYZW]}}, {{T[0-9]\.[XYZW]}},
49 ; EG-DAG: FMA {{\*? *}}[[RES]].X
50 ; EG-DAG: FMA {{\*? *}}[[RES]].Y
51 ; EG-DAG: FMA {{\*? *}}[[RES]].Z
52 ; EG-DAG: FMA {{\*? *}}[[RES]].W
Dsext-eliminate.ll6 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
7 ; EG: SUB_INT {{[* ]*}}[[RES]]
18 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
19 ; EG: ADD_INT {{[* ]*}}[[RES]]
Dsext-in-reg.ll14 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
15 ; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1
30 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
32 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
48 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
50 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
66 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
68 ; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
270 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
274 ; EG: ASHR [[RES]]
[all …]
/external/llvm/test/CodeGen/X86/
Dcodegen-prepare-extload.ll37 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
40 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
41 ; OPTALL: store i32 [[RES]], i32* %q
63 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
65 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
66 ; OPTALL: store i32 [[RES]], i32* %q
97 ; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
100 ; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
103 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
105 ; OPTALL: store i32 [[RES]], i32* %q
[all …]
Dfast-isel-select.ll8 ; CHECK: subb {{%[a-z0-9]+}}, [[RES:%[a-z0-9]+]]
9 ; CHECK: testb $1, [[RES]]
D2010-05-03-CoalescerSubRegClobber.ll25 ; CHECK: imulq %r{{.}}x, %r[[RES:..]]
26 ; CHECK-NOT: movl {{.*}}, %e[[RES]]
/external/valgrind/none/tests/ppc64/
Dopcodes.h28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ argument
35 "(" #RES "<<" X20_RES_OFFSET ")"
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) argument
/external/valgrind/none/tests/ppc32/
Dopcodes.h28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ argument
35 "(" #RES "<<" X20_RES_OFFSET ")"
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) argument
/external/valgrind/coregrind/m_syswrap/
Dsyswrap-linux.c632 if (RES == 0) { in POST()
651 if (RES == 0) { in POST()
686 if (RES == 0) { in POST()
705 if (RES == 0) { in POST()
801 if (RES == 0) in POST()
1230 if (!ML_(fd_allowed)(RES, "futex", tid, True)) { in POST()
1231 VG_(close)(RES); in POST()
1235 ML_(record_fd_open_nameless)(tid, RES); in POST()
1323 if (RES > 0) { in POST()
1344 if (!ML_(fd_allowed)(RES, "epoll_create", tid, True)) { in POST()
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Dsyswrap-tilegx-linux.c731 r = ML_(generic_POST_sys_socket)(tid, VG_(mk_SysRes_Success)(RES)); in POST()
755 ML_(linux_POST_sys_getsockopt)(tid, VG_(mk_SysRes_Success)(RES), in POST()
780 r = ML_(generic_POST_sys_accept)(tid, VG_(mk_SysRes_Success)(RES), in POST()
797 r = ML_(generic_POST_sys_accept)(tid, VG_(mk_SysRes_Success)(RES), in POST()
827 ML_(generic_POST_sys_recvfrom)(tid, VG_(mk_SysRes_Success)(RES), in POST()
850 ML_(generic_POST_sys_recvmsg)(tid, "msg", (struct vki_msghdr *)ARG2, RES); in POST()
884 ML_(generic_POST_sys_getsockname)(tid, VG_(mk_SysRes_Success)(RES), in POST()
898 ML_(generic_POST_sys_getpeername)(tid, VG_(mk_SysRes_Success)(RES), in POST()
912 ML_(generic_POST_sys_socketpair)(tid, VG_(mk_SysRes_Success)(RES), in POST()
973 ML_(generic_POST_sys_semctl)(tid, RES,ARG1,ARG2,ARG3|VKI_IPC_64,ARG4); in POST()
[all …]
Dsyswrap-generic.c2404 if (RES == 0 && ctrl && ctrl->len > 0) { in POST()
2407 if (RES == 0 && data && data->len > 0) { in POST()
2643 if (RES > 0) { in POST()
2644 POST_MEM_WRITE( ARG2, RES ); in POST()
3088 if (!ML_(fd_allowed)(RES, "dup", tid, True)) { in POST()
3089 VG_(close)(RES); in POST()
3093 ML_(record_fd_open_named)(tid, RES); in POST()
3109 ML_(record_fd_open_named)(tid, RES); in POST()
3171 is_child = ( RES == 0 ? True : False ); in PRE()
3172 child_pid = ( is_child ? -1 : RES ); in PRE()
[all …]
Dsyswrap-darwin.c1363 if (RES == 0 && ARG3 ) { in POST()
1647 if (!ML_(fd_allowed)(RES, "fcntl(DUPFD)", tid, True)) { in POST()
1648 VG_(close)(RES); in POST()
1652 ML_(record_fd_open_named)(tid, RES); in POST()
1753 ML_(generic_POST_sys_semctl)(tid, RES,ARG1,ARG2,ARG3,ARG4); in POST()
1838 if (!ML_(fd_allowed)(RES, "kqueue", tid, True)) { in POST()
1839 VG_(close)(RES); in POST()
1843 ML_(record_fd_open_with_given_name)(tid, RES, NULL); in POST()
1868 if (!ML_(fd_allowed)(RES, "guarded_kqueue_np", tid, True)) { in POST()
1869 VG_(close)(RES); in POST()
[all …]
/external/tcpdump/tests/
Ddcb_ets.out42 Willing:0, CBS:0, RES:0, Max TCs:0
56 RES: 0
139 Willing:0, CBS:0, RES:0, Max TCs:0
153 RES: 0
223 Willing:0, CBS:0, RES:0, Max TCs:0
237 RES: 0
321 Willing:0, CBS:0, RES:0, Max TCs:0
335 RES: 0
376 Willing:0, CBS:0, RES:0, Max TCs:0
390 RES: 0
[all …]
Ddcb_pfc.out41 Willing: 0, MBC: 0, RES: 0, PFC cap:4
75 Willing: 0, MBC: 0, RES: 0, PFC cap:4
109 Willing: 0, MBC: 0, RES: 0, PFC cap:4
143 Willing: 0, MBC: 0, RES: 0, PFC cap:4
/external/llvm/test/CodeGen/AArch64/
Darm64-codegen-prepare-extload.ll31 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2
34 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
35 ; OPTALL: store i32 [[RES]], i32* %q
57 ; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2
59 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32
60 ; OPTALL: store i32 [[RES]], i32* %q
91 ; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]]
94 ; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
97 ; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32
99 ; OPTALL: store i32 [[RES]], i32* %q
[all …]
Dfp16-v4-instructions.ll8 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
9 ; CHECK: fcvtn v0.4h, [[RES]]
29 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
30 ; CHECK: fcvtn v0.4h, [[RES]]
41 ; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
42 ; CHECK: fcvtn v0.4h, [[RES]]
53 ; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
54 ; CHECK: fcvtn v0.4h, [[RES]]
/external/compiler-rt/lib/tsan/
Dcheck_analyze.sh4 RES=$(./analyze_libtsan.sh)
6 printf "%s\n" "$RES"
/external/compiler-rt/test/tsan/
Dtest_output.sh26 RES=$($EXE 2>&1 || true)
27 printf "%s\n" "$RES" | $FILECHECK $SRC
/external/llvm/test/Transforms/LowerAtomic/
Datomic-swap.ll13 ; CHECK-NEXT: [[RES:%[a-z0-9]+]] = insertvalue { i8, i1 } [[TMP]], i1 [[SAME]], 1
14 ; CHECK-NEXT: [[VAL:%[a-z0-9]+]] = extractvalue { i8, i1 } [[RES]], 0

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