Searched refs:ADCS (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/test/CodeGen/ARM/ |
| D | copy-cpsr.ll | 6 ; escape. However, for long ADCS chains (and last ditch fallback) the dependency
12 ; + We want 2 long ADCS chains
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| /external/llvm/test/CodeGen/AArch64/ |
| D | nzcv-save.ll | 6 ; DAG ends up with two uses for the flags from an ADCS node, which means they
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 396 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
397 ADCS r5, r5, r1 // Should choose narrow
398 ADCS r3, r1, r3 // Should choose narrow - commutative
399 ADCS.W r2, r2, r1 // Explicitly wide
400 ADCS.W r3, r1, r3
402 ADCS r7, r7, r1 // Should use narrow
403 ADCS r7, r1, r7 // Commutative
404 ADCS r8, r1, r8 // high registers so must use wide encoding
405 ADCS r8, r8, r1
406 ADCS r5, r8, r5
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 57 ADCS, enumerator
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| D | AArch64ISelLowering.cpp | 800 case AArch64ISD::ADCS: return "AArch64ISD::ADCS"; in getTargetNodeName()
1464 Opc = AArch64ISD::ADCS; in LowerADDC_ADDE_SUBC_SUBE()
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| D | AArch64InstrInfo.td | 160 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_T2_32.c | 88 #define ADCS 0x4140 macro
737 return push_inst16(compiler, ADCS | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 21 ### ADCS ### subsection
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