| /external/libedit/src/ |
| D | keymacro.c | 628 #define ADDC(c) \ macro
644 ADDC(sep[0]); in keymacro__decode_str()
647 ADDC('^'); in keymacro__decode_str()
648 ADDC('@'); in keymacro__decode_str()
665 ADDC(sep[1]); in keymacro__decode_str()
667 ADDC('\0'); in keymacro__decode_str()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 205 ADDC, SUBC, enumerator
|
| D | SelectionDAG.h | 1057 case ISD::ADDC:
|
| /external/pcre/dist/sljit/ |
| D | sljitNativeSPARC_32.c | 100 …return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(… in emit_single_op()
|
| D | sljitNativePPC_32.c | 119 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| D | sljitNativePPC_64.c | 240 return push_inst(compiler, ADDC | OERC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| D | sljitNativeSPARC_common.c | 119 #define ADDC (OPC1(0x2) | OPC3(0x08)) macro
|
| D | sljitNativePPC_common.c | 133 #define ADDC (HI(31) | LO(10)) macro
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 262 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode()
|
| D | MipsSEISelDAGToDAG.cpp | 235 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 114 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
214 setOperationAction(ISD::ADDC, MVT::Other, Expand); in InitAMDILLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1309 case ISD::ADDC: in ExpandIntegerResult()
1375 TLI.isOperationLegalOrCustom(ISD::ADDC, in ExpandShiftByConstant()
1380 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps); in ExpandShiftByConstant()
1625 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
1631 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
1679 if (N->getOpcode() == ISD::ADDC) { in ExpandIntRes_ADDSUBC()
1680 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
|
| D | SelectionDAGDumper.cpp | 210 case ISD::ADDC: return "addc"; in getOperationName()
|
| D | DAGCombiner.cpp | 1307 case ISD::ADDC: return visitADDC(N); in visit()
1763 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0); in visitADDC()
1803 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); in visitADDE()
2771 APInt ADDC = ADDI->getAPIntValue(); in visitANDLike() local
2772 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { in visitANDLike()
2781 ADDC |= Mask; in visitANDLike()
2782 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { in visitANDLike()
2785 N0.getOperand(0), DAG.getConstant(ADDC, VT)); in visitANDLike()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 72 ADDC, // Add with carry enumerator
|
| D | ARMISelLowering.cpp | 586 setTargetDAGCombine(ISD::ADDC); in ARMTargetLowering()
684 setOperationAction(ISD::ADDC, MVT::i32, Custom); in ARMTargetLowering()
1039 case ARMISD::ADDC: return "ARMISD::ADDC"; in getTargetNodeName()
6137 case ISD::ADDC: Opc = ARMISD::ADDC; break; in LowerADDC_ADDE_SUBC_SUBE()
6316 case ISD::ADDC: in LowerOperation()
7873 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC"); in AddCombineTo64bitMLAL()
9798 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget); in PerformDAGCombine()
10398 case ARMISD::ADDC: in computeKnownBitsForTargetNode()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 126 setOperationAction(ISD::ADDC, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1711 setOperationAction(ISD::ADDC, MVT::i8, Expand); in HexagonTargetLowering()
1712 setOperationAction(ISD::ADDC, MVT::i16, Expand); in HexagonTargetLowering()
1713 setOperationAction(ISD::ADDC, MVT::i32, Expand); in HexagonTargetLowering()
1714 setOperationAction(ISD::ADDC, MVT::i64, Expand); in HexagonTargetLowering()
|
| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 71 setOperationAction(ISD::ADDC, MVT::i32, Legal); in SITargetLowering()
833 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue), in LowerGlobalAddress()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 430 let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1461 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
2695 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2829 case ISD::ADDC: in LowerOperation()
|
| D | SparcInstrInfo.td | 520 defm ADDC : F3_12np<"addx", 0b001000>;
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 365 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 95 setOperationAction(ISD::ADDC, MVT::i32, Expand); in XCoreTargetLowering()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 224 setOperationAction(ISD::ADDC, MVT::i32, Custom); in AArch64TargetLowering()
228 setOperationAction(ISD::ADDC, MVT::i64, Custom); in AArch64TargetLowering()
1457 case ISD::ADDC: in LowerADDC_ADDE_SUBC_SUBE()
1950 case ISD::ADDC: in LowerOperation()
|