| /external/clang/test/Layout/ |
| D | ms-x86-primary-bases.cpp | 167 struct AX : B0X, B1X { int a; AX() : a(0xf000000A) {} virtual void f() { printf("A"); } }; in f() struct
324 sizeof(AX)+
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| D | ms-x86-aligned-tail-padding.cpp | 352 struct AX : B0X, virtual B2X, virtual B6X, virtual B3X { struct
354 AX() : a(0xf000000A) {} in AX() argument
531 sizeof(AX)+
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| D | ms-x86-lazy-empty-nonvirtual-base.cpp | 623 struct AX : B1X, B2X, B3X, B4X, virtual B0X { struct
625 AX() : a(0x0000000A) { printf(" A = %p\n", this); } in AX() argument
831 sizeof(AX)+
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| /external/llvm/test/MC/X86/ |
| D | intel-syntax.s | 415 div AX, BX
423 idiv AX, BX
455 xchg AX, CX
456 xchg CX, AX
468 xchg AX, [ECX]
469 xchg [ECX], AX
483 test AX, [ECX]
484 test [ECX], AX
493 fnstsw AX
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 57 // AL is really implied by AX, but the registers in Defs must match the
60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
67 // AX,DX = AX*GR16
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
93 // AX,DX = AX*[mem16]
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
115 // AX,DX = AX*GR16
116 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
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| D | X86InstrExtension.td | 15 let Defs = [AX], Uses = [AL] in
17 "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
18 let Defs = [EAX], Uses = [AX] in
20 "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
22 let Defs = [AX,DX], Uses = [AX] in
24 "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
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| D | X86RegisterInfo.cpp | 600 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
612 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
649 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
650 return X86::AX; in getX86SubSuperRegister()
685 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
721 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
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| D | X86RegisterInfo.td | 39 // AL aliases AX if we tell it that AX aliased AL (for example).
78 def AX : X86Reg<"ax", 0, [AL,AH]>;
105 def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
333 (add AX, CX, DX, SI, DI, BX, BP, SP,
366 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
385 (add AX, CX, DX, SI, DI, BX, BP, SP)>;
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| /external/llvm/test/CodeGen/X86/ |
| D | crash-O0.ll | 9 ; aliased registers (AX and AL) - RegAllocFast does not like that.
34 ; CQO defines implicitly AX and DIV64 uses it implicitly too.
36 ; AX for the vreg defined in between and the compiler crashed.
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| D | pr21792.ll | 36 ; CHECK-NEXT: movd %xmm0, %r[[AX:..]]
37 ; CHECK-NEXT: movslq %e[[AX]],
38 ; CHECK-NEXT: sarq $32, %r[[AX]]
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| D | inline-asm.ll | 4 ; Dest is AX, dest type = i32.
10 ; input is AX, in type = i32.
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| D | 2010-02-23-DIV8rDefinesAX.ll | 4 ; This test produces a DIV8r instruction and uses %AX instead of %AH and %AL.
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| D | 2010-03-04-Mul8Bug.ll | 5 ; from the AX register instead of AH/AL. That confuses live interval analysis.
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| /external/libpcap/msdos/ |
| D | pkt_rx1.s | 71 ; 1st time (AX=0) it requests an address where to put the packet
73 ; 2nd time (AX=1) the packet has been copied to this location (DS:SI)
93 cmp ax, 0 ; first call? (AX=0)
94 jne @post ; AX=1: second call, do post process
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| D | pkt_rx0.asm | 115 ; 1st time (AX=0) it requests an address where to put the packet
117 ; 2nd time (AX=1) the packet has been copied to this location (DS:SI)
142 cmp ax, 0 ; first call? (AX=0)
143 jne @post ; AX=1: second call, do post process
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| /external/clang/test/SemaCXX/ |
| D | overloaded-operator.cpp | 268 struct AX { struct
269 AX& operator ->(); // expected-note {{declared here}}
274 AX a; in m() argument
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| /external/icu/icu4c/source/data/region/ |
| D | ur_IN.txt | 12 AX{"جزائر آلینڈ"}
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| /external/eigen/unsupported/Eigen/src/MatrixFunctions/ |
| D | MatrixFunction.h | 453 Scalar AX; in solveTriangularSylvester() local
455 AX = 0; in solveTriangularSylvester()
458 AX = AXmatrix(0,0); in solveTriangularSylvester()
470 X(i,j) = (C(i,j) - AX - XB) / (A(i,i) + B(j,j)); in solveTriangularSylvester()
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| /external/jpeg/ |
| D | jmemdosa.asm | 259 ; The XMScontext structure contains values for the AX,DX,BX,SI,DS registers.
261 ; AX,DX,BX registers are written back to the context structure.
340 ; The EMScontext structure contains values for the AX,DX,BX,SI,DS registers.
342 ; AX,DX,BX registers are written back to the context structure.
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| /external/pcre/dist/testdata/ |
| D | testoutput10 | 1232 0: AX
1243 AX
1250 0: AX
1272 0: AX
1298 0: AX
1320 0: AX
1331 AX
1338 0: AX
1360 0: AX
1386 0: AX
[all …]
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| D | testoutput4 | 714 AX
715 0: AX
728 AX
729 0: AX
744 AX
745 0: AX
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| D | testoutput6 | 741 0: AX
752 AX
759 0: AX
781 0: AX
807 0: AX
829 0: AX
840 AX
847 0: AX
869 0: AX
895 0: AX
[all …]
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/fr-FR/ |
| D | fr-FR_nk0_kdt_lfz5.pkb | 35 …���H>Ն`�q-� 6��p�AW��iY=�q(��w�Y�;8��l3�q�kB@ f,*PZ�ä�d*s^�, ^��]�0�AX�r`�R 4��r`Ս��@6�Q�\…
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 41 def AX;
139 [(set AX, (signext AL))]>;
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-US/ |
| D | en-US_lh0_kdt_lfz5.pkb | 51 a�<({�y�l��&BI|�A�F�B�(+I�z�W���ϓH}�L ����� ې�#�m�N�|�zd ���4������Z0l �����$���\pLs~�AX…
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