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Searched refs:AddDReg (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp869 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg() function in ARMBaseInstrInfo
918 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
919 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
929 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
930 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
965 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
966 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
967 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI); in storeRegToStackSlot()
986 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
987 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); in storeRegToStackSlot()
[all …]
DThumb2InstrInfo.cpp157 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
158 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot()
198 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
199 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
DARMBaseInstrInfo.h195 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,