Searched refs:AddRegFrm (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
93 "mov $dst, $src", 0xB0, AddRegFrm,
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 236 AddRegFrm = 2, enumerator
669 case X86II::AddRegFrm: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 1307 case X86II::AddRegFrm: in EncodeInstruction()
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 96 AddRegFrm = 2, enumerator
597 case X86Local::AddRegFrm: in emitInstructionSpecifier()
885 if (Form == X86Local::AddRegFrm) { in emitDecodePath()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 991 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
993 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1006 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1008 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1052 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1060 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1105 def BSWAP32r : I<0xC8, AddRegFrm,
1110 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1238 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1241 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
[all …]
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| D | X86InstrArithmetic.td | 475 def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
478 def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
521 def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
524 def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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| D | X86RegisterInfo.td | 393 // GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit
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| D | X86InstrFormats.td | 22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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| D | X86InstrCompiler.td | 267 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1805 case X86II::AddRegFrm: // for instructions that have one register operand
1840 for the ``X86II::AddRegFrm`` case, the first data emitted (by ``emitByte``) is
1851 case X86II::AddRegFrm:
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