| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 176 BUILD_PAIR, enumerator
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
703 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
718 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
758 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in ExpandADDSUB()
1805 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 282 case ISD::BUILD_PAIR: return "build_pair"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 64 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
126 return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), in SoftenFloatRes_BUILD_PAIR()
880 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandFloatResult()
1312 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); in ExpandFloatRes_XINT_TO_FP()
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| D | LegalizeTypesGeneric.cpp | 137 Vals.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, in ExpandRes_BITCAST()
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| D | LegalizeIntegerTypes.cpp | 57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
839 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; in PromoteIntegerOperand()
1235 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | SelectionDAGBuilder.cpp | 149 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
179 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
7665 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { in LowerArguments()
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| D | TargetLowering.cpp | 864 case ISD::BUILD_PAIR: { in SimplifyDemandedBits()
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| D | SelectionDAG.cpp | 736 case ISD::BUILD_PAIR: { in VerifySDNode()
3437 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
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| D | DAGCombiner.cpp | 1347 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); in visit()
6765 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
6925 if (N0.getOpcode() == ISD::BUILD_PAIR) { in visitBITCAST()
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| D | LegalizeDAG.cpp | 3757 case ISD::BUILD_PAIR: { in ExpandNode()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 1667 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero); in LowerUDIVREM64()
1668 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero); in LowerUDIVREM64()
1679 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero); in LowerUDIVREM64()
1709 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi); in LowerUDIVREM64()
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| D | AMDGPUISelDAGToDAG.cpp | 375 case ISD::BUILD_PAIR: { in Select()
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| D | SIISelLowering.cpp | 838 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in LowerGlobalAddress()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 399 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
454 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1609 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 1295 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in extractLOHI()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4044 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
4343 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
6255 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, in ReplaceREADCYCLECOUNTER()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
4917 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
7778 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 11912 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops) in FP_TO_INTHelper()
15181 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops); in getReadPerformanceCounter()
15235 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops); in getReadTimeStampCounter()
17438 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF)); in ReplaceNodeResults()
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