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Searched refs:BuildMI (Results 1 – 25 of 144) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp106 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
109 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
149 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
152 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
190 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
193 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
227 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
230 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
253 BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
256 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add), in runOnMachineFunction()
[all …]
DHexagonSplitConst32AndConst64.cpp89 BuildMI (*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
102 BuildMI (*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
104 BuildMI (*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
126 BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
151 BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
153 BuildMI (*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
/external/llvm/lib/Target/R600/
DSILowerControlFlow.cpp141 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
160 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in SkipIfDead()
165 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) in SkipIfDead()
177 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in SkipIfDead()
186 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
189 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
204 BuildMI(MBB, MBB.getFirstNonPHI(), DL, in Else()
208 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in Else()
224 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in Break()
239 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in IfBreak()
[all …]
DSIInstrInfo.cpp338 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) in copyPhysReg()
345 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) in copyPhysReg()
350 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC) in copyPhysReg()
359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) in copyPhysReg()
381 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
419 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, in copyPhysReg()
499 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
510 BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) in storeRegToStackSlot()
547 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
558 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg); in loadRegFromStackSlot()
[all …]
/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp222 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
296 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
317 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
320 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) in expandToLongBranch()
321 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
328 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
330 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
335 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) in expandToLongBranch()
336 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
[all …]
DMipsSEInstrInfo.cpp107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) in copyPhysReg()
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
218 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
259 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
371 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); in adjustStackPtr()
374 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); in adjustStackPtr()
406 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); in loadImmediate()
408 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
413 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) in loadImmediate()
[all …]
DMipsSEFrameLowering.cpp160 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
174 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
198 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
200 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
220 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
222 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
253 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
254 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
256 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
257 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h235 inline MachineInstrBuilder BuildMI(MachineFunction &MF, in BuildMI() function
244 inline MachineInstrBuilder BuildMI(MachineFunction &MF, in BuildMI() function
256 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
267 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
278 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
285 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
289 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
296 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
306 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
316 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp352 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
356 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
361 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
365 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
370 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
374 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
378 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
689 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); in emitPrologue()
699 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); in emitPrologue()
706 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
[all …]
DPPCRegisterInfo.cpp357 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
361 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
365 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
382 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in lowerDynamicAlloc()
387 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in lowerDynamicAlloc()
393 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
397 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
407 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in lowerDynamicAlloc()
412 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in lowerDynamicAlloc()
418 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) in lowerDynamicAlloc()
[all …]
DPPCBranchSelector.cpp197 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) in runOnMachineFunction()
201 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
204 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); in runOnMachineFunction()
206 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
208 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
210 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
212 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); in runOnMachineFunction()
218 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest); in runOnMachineFunction()
DPPCFastISel.cpp413 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8), in PPCSimplifyAddress()
517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
525 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
549 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
647 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in PPCEmitStore()
658 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in PPCEmitStore()
679 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in PPCEmitStore()
752 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC)) in SelectBranch()
862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
[all …]
DPPCInstrInfo.cpp282 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) in commuteInstruction()
336 BuildMI(MBB, MI, DL, get(Opcode)); in insertNoop()
562 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in InsertBranch()
564 BuildMI(&MBB, DL, get(Cond[0].getImm() ? in InsertBranch()
568 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
570 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
572 BuildMI(&MBB, DL, get(PPC::BCC)) in InsertBranch()
579 BuildMI(&MBB, DL, get(Cond[0].getImm() ? in InsertBranch()
583 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
585 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
[all …]
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp239 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg) in emitSPUpdate()
244 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
263 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
275 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), in emitSPUpdate()
278 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
374 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitCalleeSavedFrameMoves()
430 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11) in emitStackProbeCall()
432 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11); in emitStackProbeCall()
434 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol); in emitStackProbeCall()
449 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP) in emitStackProbeCall()
[all …]
/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp209 BuildMI(MBB, std::next(Info.I), dl, in emitDefCFAOffsets()
249 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
254 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
263 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
267 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
275 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
440 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
444 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
453 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
461 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
[all …]
DThumb1FrameLowering.cpp122 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
134 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
227 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
239 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
246 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
253 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
271 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
295 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) in emitPrologue()
371 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitEpilogue()
[all …]
DARMFastISel.cpp296 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, in fastEmitInst_r()
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) in fastEmitInst_r()
301 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, in fastEmitInst_r()
322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
326 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) in fastEmitInst_rr()
329 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, in fastEmitInst_rr()
352 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rrr()
357 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) in fastEmitInst_rrr()
361 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, in fastEmitInst_rrr()
380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_ri()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) in AnalyzeBranch()
207 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) in AnalyzeBranch()
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in InsertBranch()
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in InsertBranch()
295 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
298 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
302 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
313 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
[all …]
DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
116 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
121 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
129 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp67 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
99 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
136 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
157 BuildMI(MBB, MBBI, DL, in emitEpilogue()
161 BuildMI(MBB, MBBI, DL, in emitEpilogue()
171 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
200 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
221 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); in restoreCalleeSavedRegisters()
248 New = BuildMI(MF, Old->getDebugLoc(), in eliminateCallFramePseudoInstr()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp44 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg) in copyPhysReg()
47 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg) in copyPhysReg()
50 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg) in copyPhysReg()
53 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg) in copyPhysReg()
56 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg) in copyPhysReg()
59 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg) in copyPhysReg()
260 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB); in InsertBranch()
262 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in InsertBranch()
268 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in InsertBranch()
269 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB); in InsertBranch()
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
177 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0); in InsertSPConstInst()
[all …]
DXCoreInstrInfo.cpp294 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); in InsertBranch()
298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
307 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
309 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); in InsertBranch()
349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
361 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) in copyPhysReg()
385 BuildMI(MBB, I, DL, get(XCore::STWFI)) in storeRegToStackSlot()
408 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()
449 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg) in loadImmediate()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) in EmitInstrWithCustomInserter()
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) in EmitInstrWithCustomInserter()
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) in EmitInstrWithCustomInserter()
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY)) in EmitInstrWithCustomInserter()
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32), in EmitInstrWithCustomInserter()
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr) in EmitInstrWithCustomInserter()
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode())) in EmitInstrWithCustomInserter()
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0) in EmitInstrWithCustomInserter()
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1) in EmitInstrWithCustomInserter()
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)) in EmitInstrWithCustomInserter()
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DSIISelLowering.cpp82 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) in EmitInstrWithCustomInserter()
97 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) in EmitInstrWithCustomInserter()
112 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) in EmitInstrWithCustomInserter()
145 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT)) in AppendS_WAITCNT()
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP()
164 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp) in LowerSI_INTERP()
170 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32)) in LowerSI_INTERP()
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP_CONST()
194 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32)) in LowerSI_INTERP_CONST()
207 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMPX_LE_F32_e32), in LowerSI_KIL()
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