| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.cpp | 837 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in fromString() local
842 Ops[4].getAsInteger(10, CRm); in fromString()
844 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in fromString()
871 uint32_t CRm = (Bits >> 3) & 0xf; in toString() local
875 + "_c" + utostr(CRm) + "_" + utostr(Op2); in toString()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 4736 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4737 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4739 imm:$CRm, imm:$opc2)]>,
4746 bits<4> CRm;
4748 let Inst{3-0} = CRm;
4758 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4759 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4761 imm:$CRm, imm:$opc2)]>,
4769 bits<4> CRm;
4771 let Inst{3-0} = CRm;
[all …]
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| D | ARMInstrThumb2.td | 4121 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4131 bits<4> CRm;
4138 let Inst{3-0} = CRm;
4145 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4146 opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4155 bits<4> CRm;
4161 let Inst{3-0} = CRm;
4168 c_imm:$CRm, imm0_7:$opc2),
4170 imm:$CRm, imm:$opc2)]>,
4172 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
[all …]
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| /external/vixl/src/vixl/a64/ |
| D | disasm-a64.cc | 1291 form = (instr->CRm() == 0xf) ? NULL : "'IX"; in VisitSystem()
3149 AppendToOutput("#0x%" PRIx64, instr->CRm()); in SubstituteImmediateField()
3456 case 'm': cr = instr->CRm(); break; in SubstituteCrField()
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| D | constants-a64.h | 135 V_(CRm, 11, 8, Bits) \
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| D | assembler-a64.cc | 1874 Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(rt)); in sys()
2523 Emit(CLREX | CRm(imm4)); in clrex()
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| D | assembler-a64.h | 3920 static Instr CRm(int imm4) { in CRm() function
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 204 V_(CRm, 11, 8, Bits) \
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 806 // Hint instructions that take both a CRm and a 3-bit immediate.
820 // CRm. op2 differentiates the opcodes.
831 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
833 bits<4> CRm;
835 let Inst{11-8} = CRm;
846 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
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| D | AArch64InstrInfo.td | 372 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
375 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
378 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 5150 unsigned CRm = fieldFromInstruction(Val, 0, 4); in DecodeMRRC2() local
5168 Inst.addOperand(MCOperand::CreateImm(CRm)); in DecodeMRRC2()
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| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 6813 UInt CRm = INSN(11,8); in dis_ARM64_branch_etc() local
6814 vassert(opc <= 2 && CRm <= 15); in dis_ARM64_branch_etc()
6821 DIP("%s %s\n", opNames[opc], howNames[CRm]); in dis_ARM64_branch_etc()
|