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Searched refs:CTX_RB3D_CNTL (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state_init.c334 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); in ctx_emit_cs()
336 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; in ctx_emit_cs()
339 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; in ctx_emit_cs()
342 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; in ctx_emit_cs()
345 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; in ctx_emit_cs()
387 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); in ctx_emit_cs()
703 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE | in radeonInitState()
708 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; in radeonInitState()
711 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; in radeonInitState()
721 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; in radeonInitState()
[all …]
Dradeon_state.c142 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
144 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
1528 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ALPHA_BLEND_ENABLE; in radeonEnable()
1530 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ALPHA_BLEND_ENABLE; in radeonEnable()
1534 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE; in radeonEnable()
1536 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE; in radeonEnable()
1585 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_Z_ENABLE; in radeonEnable()
1587 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_Z_ENABLE; in radeonEnable()
1594 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; in radeonEnable()
1595 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable; in radeonEnable()
[all …]
Dradeon_context.h99 #define CTX_RB3D_CNTL 10 macro
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_state.c205 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & in r200_set_blend_state()
218 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; in r200_set_blend_state()
223 … rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE; in r200_set_blend_state()
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl; in r200_set_blend_state()
682 GLuint flag = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & ~R200_PLANE_MASK_ENABLE; in r200ColorMask()
697 if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) { in r200ColorMask()
699 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag; in r200ColorMask()
1777 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_Z_ENABLE; in r200Enable()
1779 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_Z_ENABLE; in r200Enable()
1786 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; in r200Enable()
[all …]
Dr200_state_init.c451 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); in ctx_emit_cs()
453 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; in ctx_emit_cs()
456 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; in ctx_emit_cs()
459 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; in ctx_emit_cs()
462 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; in ctx_emit_cs()
505 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); in ctx_emit_cs()
963 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; in r200InitState()
966 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; in r200InitState()
976 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; in r200InitState()
978 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; in r200InitState()
Dr200_context.h108 #define CTX_RB3D_CNTL 10 macro