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Searched refs:CTX_RB3D_ZSTENCILCNTL (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state.c266 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK; in radeonDepthFunc()
270 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEVER; in radeonDepthFunc()
273 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LESS; in radeonDepthFunc()
276 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_EQUAL; in radeonDepthFunc()
279 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LEQUAL; in radeonDepthFunc()
282 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GREATER; in radeonDepthFunc()
285 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEQUAL; in radeonDepthFunc()
288 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GEQUAL; in radeonDepthFunc()
291 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_ALWAYS; in radeonDepthFunc()
303 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_WRITE_ENABLE; in radeonDepthMask()
[all …]
Dradeon_state_init.c364 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; in ctx_emit_cs()
365 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; in ctx_emit_cs()
384 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); in ctx_emit_cs()
682 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS | in radeonInitState()
690 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE | in radeonInitState()
696 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY; in radeonInitState()
Dradeon_context.h96 #define CTX_RB3D_ZSTENCILCNTL 7 macro
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_state.c328 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~R200_Z_TEST_MASK; in r200DepthFunc()
332 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_NEVER; in r200DepthFunc()
335 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_LESS; in r200DepthFunc()
338 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_EQUAL; in r200DepthFunc()
341 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_LEQUAL; in r200DepthFunc()
344 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_GREATER; in r200DepthFunc()
347 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_NEQUAL; in r200DepthFunc()
350 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_GEQUAL; in r200DepthFunc()
353 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_ALWAYS; in r200DepthFunc()
364 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_WRITE_ENABLE; in r200DepthMask()
[all …]
Dr200_state_init.c482 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; in ctx_emit_cs()
483 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; in ctx_emit_cs()
502 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); in ctx_emit_cs()
944 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS | in r200InitState()
952 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | in r200InitState()
Dr200_context.h105 #define CTX_RB3D_ZSTENCILCNTL 7 macro