1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 #include "MipsISelLowering.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsCCState.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/CodeGen/ValueTypes.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include <cctype>
40
41 using namespace llvm;
42
43 #define DEBUG_TYPE "mips-lower"
44
45 STATISTIC(NumTailCalls, "Number of tail calls");
46
47 static cl::opt<bool>
48 LargeGOT("mxgot", cl::Hidden,
49 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
50
51 static cl::opt<bool>
52 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
53 cl::desc("MIPS: Don't trap on integer division by zero."),
54 cl::init(false));
55
56 cl::opt<bool>
57 EnableMipsFastISel("mips-fast-isel", cl::Hidden,
58 cl::desc("Allow mips-fast-isel to be used"),
59 cl::init(false));
60
61 static const MCPhysReg Mips64DPRegs[8] = {
62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
64 };
65
66 // If I is a shifted mask, set the size (Size) and the first bit of the
67 // mask (Pos), and return true.
68 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
isShiftedMask(uint64_t I,uint64_t & Pos,uint64_t & Size)69 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
70 if (!isShiftedMask_64(I))
71 return false;
72
73 Size = countPopulation(I);
74 Pos = countTrailingZeros(I);
75 return true;
76 }
77
getGlobalReg(SelectionDAG & DAG,EVT Ty) const78 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
81 }
82
getTargetNode(GlobalAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const83 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
84 SelectionDAG &DAG,
85 unsigned Flag) const {
86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
87 }
88
getTargetNode(ExternalSymbolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const89 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
90 SelectionDAG &DAG,
91 unsigned Flag) const {
92 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
93 }
94
getTargetNode(BlockAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const95 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
96 SelectionDAG &DAG,
97 unsigned Flag) const {
98 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
99 }
100
getTargetNode(JumpTableSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const101 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
102 SelectionDAG &DAG,
103 unsigned Flag) const {
104 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
105 }
106
getTargetNode(ConstantPoolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const107 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
108 SelectionDAG &DAG,
109 unsigned Flag) const {
110 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
111 N->getOffset(), Flag);
112 }
113
getTargetNodeName(unsigned Opcode) const114 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
115 switch (Opcode) {
116 case MipsISD::JmpLink: return "MipsISD::JmpLink";
117 case MipsISD::TailCall: return "MipsISD::TailCall";
118 case MipsISD::Hi: return "MipsISD::Hi";
119 case MipsISD::Lo: return "MipsISD::Lo";
120 case MipsISD::GPRel: return "MipsISD::GPRel";
121 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
122 case MipsISD::Ret: return "MipsISD::Ret";
123 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
124 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
125 case MipsISD::FPCmp: return "MipsISD::FPCmp";
126 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
127 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
128 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
129 case MipsISD::MFHI: return "MipsISD::MFHI";
130 case MipsISD::MFLO: return "MipsISD::MFLO";
131 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
132 case MipsISD::Mult: return "MipsISD::Mult";
133 case MipsISD::Multu: return "MipsISD::Multu";
134 case MipsISD::MAdd: return "MipsISD::MAdd";
135 case MipsISD::MAddu: return "MipsISD::MAddu";
136 case MipsISD::MSub: return "MipsISD::MSub";
137 case MipsISD::MSubu: return "MipsISD::MSubu";
138 case MipsISD::DivRem: return "MipsISD::DivRem";
139 case MipsISD::DivRemU: return "MipsISD::DivRemU";
140 case MipsISD::DivRem16: return "MipsISD::DivRem16";
141 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
142 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
143 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
144 case MipsISD::Wrapper: return "MipsISD::Wrapper";
145 case MipsISD::Sync: return "MipsISD::Sync";
146 case MipsISD::Ext: return "MipsISD::Ext";
147 case MipsISD::Ins: return "MipsISD::Ins";
148 case MipsISD::LWL: return "MipsISD::LWL";
149 case MipsISD::LWR: return "MipsISD::LWR";
150 case MipsISD::SWL: return "MipsISD::SWL";
151 case MipsISD::SWR: return "MipsISD::SWR";
152 case MipsISD::LDL: return "MipsISD::LDL";
153 case MipsISD::LDR: return "MipsISD::LDR";
154 case MipsISD::SDL: return "MipsISD::SDL";
155 case MipsISD::SDR: return "MipsISD::SDR";
156 case MipsISD::EXTP: return "MipsISD::EXTP";
157 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
158 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
159 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
160 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
161 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
162 case MipsISD::SHILO: return "MipsISD::SHILO";
163 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
164 case MipsISD::MULT: return "MipsISD::MULT";
165 case MipsISD::MULTU: return "MipsISD::MULTU";
166 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
167 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
168 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
169 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
170 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
171 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
172 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
173 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
174 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
175 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
176 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
177 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
178 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
179 case MipsISD::VCEQ: return "MipsISD::VCEQ";
180 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
181 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
182 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
183 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
184 case MipsISD::VSMAX: return "MipsISD::VSMAX";
185 case MipsISD::VSMIN: return "MipsISD::VSMIN";
186 case MipsISD::VUMAX: return "MipsISD::VUMAX";
187 case MipsISD::VUMIN: return "MipsISD::VUMIN";
188 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
189 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
190 case MipsISD::VNOR: return "MipsISD::VNOR";
191 case MipsISD::VSHF: return "MipsISD::VSHF";
192 case MipsISD::SHF: return "MipsISD::SHF";
193 case MipsISD::ILVEV: return "MipsISD::ILVEV";
194 case MipsISD::ILVOD: return "MipsISD::ILVOD";
195 case MipsISD::ILVL: return "MipsISD::ILVL";
196 case MipsISD::ILVR: return "MipsISD::ILVR";
197 case MipsISD::PCKEV: return "MipsISD::PCKEV";
198 case MipsISD::PCKOD: return "MipsISD::PCKOD";
199 case MipsISD::INSVE: return "MipsISD::INSVE";
200 default: return nullptr;
201 }
202 }
203
MipsTargetLowering(const MipsTargetMachine & TM,const MipsSubtarget & STI)204 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
205 const MipsSubtarget &STI)
206 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
207 // Mips does not have i1 type, so use i32 for
208 // setcc operations results (slt, sgt, ...).
209 setBooleanContents(ZeroOrOneBooleanContent);
210 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
211 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
212 // does. Integer booleans still use 0 and 1.
213 if (Subtarget.hasMips32r6())
214 setBooleanContents(ZeroOrOneBooleanContent,
215 ZeroOrNegativeOneBooleanContent);
216
217 // Load extented operations for i1 types must be promoted
218 for (MVT VT : MVT::integer_valuetypes()) {
219 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
220 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
221 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
222 }
223
224 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
225 // for f32, f16
226 for (MVT VT : MVT::fp_valuetypes()) {
227 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
229 }
230
231 // Set LoadExtAction for f16 vectors to Expand
232 for (MVT VT : MVT::fp_vector_valuetypes()) {
233 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
234 if (F16VT.isValid())
235 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
236 }
237
238 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
239 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
240
241 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
242
243 // Used by legalize types to correctly generate the setcc result.
244 // Without this, every float setcc comes with a AND/OR with the result,
245 // we don't want this, since the fpcmp result goes to a flag register,
246 // which is used implicitly by brcond and select operations.
247 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
248
249 // Mips Custom Operations
250 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
251 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
252 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
253 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
254 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
255 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
256 setOperationAction(ISD::SELECT, MVT::f32, Custom);
257 setOperationAction(ISD::SELECT, MVT::f64, Custom);
258 setOperationAction(ISD::SELECT, MVT::i32, Custom);
259 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
260 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
261 setOperationAction(ISD::SETCC, MVT::f32, Custom);
262 setOperationAction(ISD::SETCC, MVT::f64, Custom);
263 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
264 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
265 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
266 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
267
268 if (Subtarget.isGP64bit()) {
269 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
270 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
271 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
272 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
273 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
274 setOperationAction(ISD::SELECT, MVT::i64, Custom);
275 setOperationAction(ISD::LOAD, MVT::i64, Custom);
276 setOperationAction(ISD::STORE, MVT::i64, Custom);
277 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
278 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
279 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
280 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
281 }
282
283 if (!Subtarget.isGP64bit()) {
284 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
285 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
286 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
287 }
288
289 setOperationAction(ISD::ADD, MVT::i32, Custom);
290 if (Subtarget.isGP64bit())
291 setOperationAction(ISD::ADD, MVT::i64, Custom);
292
293 setOperationAction(ISD::SDIV, MVT::i32, Expand);
294 setOperationAction(ISD::SREM, MVT::i32, Expand);
295 setOperationAction(ISD::UDIV, MVT::i32, Expand);
296 setOperationAction(ISD::UREM, MVT::i32, Expand);
297 setOperationAction(ISD::SDIV, MVT::i64, Expand);
298 setOperationAction(ISD::SREM, MVT::i64, Expand);
299 setOperationAction(ISD::UDIV, MVT::i64, Expand);
300 setOperationAction(ISD::UREM, MVT::i64, Expand);
301
302 // Operations not directly supported by Mips.
303 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
304 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
305 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
306 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
307 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
309 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
310 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
311 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
312 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
314 if (Subtarget.hasCnMips()) {
315 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
316 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
317 } else {
318 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
319 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
320 }
321 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
322 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
323 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
325 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
326 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
327 setOperationAction(ISD::ROTL, MVT::i32, Expand);
328 setOperationAction(ISD::ROTL, MVT::i64, Expand);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
331
332 if (!Subtarget.hasMips32r2())
333 setOperationAction(ISD::ROTR, MVT::i32, Expand);
334
335 if (!Subtarget.hasMips64r2())
336 setOperationAction(ISD::ROTR, MVT::i64, Expand);
337
338 setOperationAction(ISD::FSIN, MVT::f32, Expand);
339 setOperationAction(ISD::FSIN, MVT::f64, Expand);
340 setOperationAction(ISD::FCOS, MVT::f32, Expand);
341 setOperationAction(ISD::FCOS, MVT::f64, Expand);
342 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
343 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
344 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
345 setOperationAction(ISD::FPOW, MVT::f32, Expand);
346 setOperationAction(ISD::FPOW, MVT::f64, Expand);
347 setOperationAction(ISD::FLOG, MVT::f32, Expand);
348 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
349 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
350 setOperationAction(ISD::FEXP, MVT::f32, Expand);
351 setOperationAction(ISD::FMA, MVT::f32, Expand);
352 setOperationAction(ISD::FMA, MVT::f64, Expand);
353 setOperationAction(ISD::FREM, MVT::f32, Expand);
354 setOperationAction(ISD::FREM, MVT::f64, Expand);
355
356 // Lower f16 conversion operations into library calls
357 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
358 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
359 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
360 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
361
362 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
363
364 setOperationAction(ISD::VASTART, MVT::Other, Custom);
365 setOperationAction(ISD::VAARG, MVT::Other, Custom);
366 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
367 setOperationAction(ISD::VAEND, MVT::Other, Expand);
368
369 // Use the default for now
370 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
371 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
372
373 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
374 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
375 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
376 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
377
378 setInsertFencesForAtomic(true);
379
380 if (!Subtarget.hasMips32r2()) {
381 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
382 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
383 }
384
385 // MIPS16 lacks MIPS32's clz and clo instructions.
386 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
387 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
388 if (!Subtarget.hasMips64())
389 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
390
391 if (!Subtarget.hasMips32r2())
392 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
393 if (!Subtarget.hasMips64r2())
394 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
395
396 if (Subtarget.isGP64bit()) {
397 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
398 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
399 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
400 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
401 }
402
403 setOperationAction(ISD::TRAP, MVT::Other, Legal);
404
405 setTargetDAGCombine(ISD::SDIVREM);
406 setTargetDAGCombine(ISD::UDIVREM);
407 setTargetDAGCombine(ISD::SELECT);
408 setTargetDAGCombine(ISD::AND);
409 setTargetDAGCombine(ISD::OR);
410 setTargetDAGCombine(ISD::ADD);
411
412 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
413
414 // The arguments on the stack are defined in terms of 4-byte slots on O32
415 // and 8-byte slots on N32/N64.
416 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
417
418 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
419
420 setExceptionPointerRegister(ABI.IsN64() ? Mips::A0_64 : Mips::A0);
421 setExceptionSelectorRegister(ABI.IsN64() ? Mips::A1_64 : Mips::A1);
422
423 MaxStoresPerMemcpy = 16;
424
425 isMicroMips = Subtarget.inMicroMipsMode();
426 }
427
create(const MipsTargetMachine & TM,const MipsSubtarget & STI)428 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
429 const MipsSubtarget &STI) {
430 if (STI.inMips16Mode())
431 return llvm::createMips16TargetLowering(TM, STI);
432
433 return llvm::createMipsSETargetLowering(TM, STI);
434 }
435
436 // Create a fast isel object.
437 FastISel *
createFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo) const438 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
439 const TargetLibraryInfo *libInfo) const {
440 if (!EnableMipsFastISel)
441 return TargetLowering::createFastISel(funcInfo, libInfo);
442 return Mips::createFastISel(funcInfo, libInfo);
443 }
444
getSetCCResultType(LLVMContext &,EVT VT) const445 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
446 if (!VT.isVector())
447 return MVT::i32;
448 return VT.changeVectorElementTypeToInteger();
449 }
450
performDivRemCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)451 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
452 TargetLowering::DAGCombinerInfo &DCI,
453 const MipsSubtarget &Subtarget) {
454 if (DCI.isBeforeLegalizeOps())
455 return SDValue();
456
457 EVT Ty = N->getValueType(0);
458 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
459 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
460 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
461 MipsISD::DivRemU16;
462 SDLoc DL(N);
463
464 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
465 N->getOperand(0), N->getOperand(1));
466 SDValue InChain = DAG.getEntryNode();
467 SDValue InGlue = DivRem;
468
469 // insert MFLO
470 if (N->hasAnyUseOfValue(0)) {
471 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
472 InGlue);
473 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
474 InChain = CopyFromLo.getValue(1);
475 InGlue = CopyFromLo.getValue(2);
476 }
477
478 // insert MFHI
479 if (N->hasAnyUseOfValue(1)) {
480 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
481 HI, Ty, InGlue);
482 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
483 }
484
485 return SDValue();
486 }
487
condCodeToFCC(ISD::CondCode CC)488 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
489 switch (CC) {
490 default: llvm_unreachable("Unknown fp condition code!");
491 case ISD::SETEQ:
492 case ISD::SETOEQ: return Mips::FCOND_OEQ;
493 case ISD::SETUNE: return Mips::FCOND_UNE;
494 case ISD::SETLT:
495 case ISD::SETOLT: return Mips::FCOND_OLT;
496 case ISD::SETGT:
497 case ISD::SETOGT: return Mips::FCOND_OGT;
498 case ISD::SETLE:
499 case ISD::SETOLE: return Mips::FCOND_OLE;
500 case ISD::SETGE:
501 case ISD::SETOGE: return Mips::FCOND_OGE;
502 case ISD::SETULT: return Mips::FCOND_ULT;
503 case ISD::SETULE: return Mips::FCOND_ULE;
504 case ISD::SETUGT: return Mips::FCOND_UGT;
505 case ISD::SETUGE: return Mips::FCOND_UGE;
506 case ISD::SETUO: return Mips::FCOND_UN;
507 case ISD::SETO: return Mips::FCOND_OR;
508 case ISD::SETNE:
509 case ISD::SETONE: return Mips::FCOND_ONE;
510 case ISD::SETUEQ: return Mips::FCOND_UEQ;
511 }
512 }
513
514
515 /// This function returns true if the floating point conditional branches and
516 /// conditional moves which use condition code CC should be inverted.
invertFPCondCodeUser(Mips::CondCode CC)517 static bool invertFPCondCodeUser(Mips::CondCode CC) {
518 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
519 return false;
520
521 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
522 "Illegal Condition Code");
523
524 return true;
525 }
526
527 // Creates and returns an FPCmp node from a setcc node.
528 // Returns Op if setcc is not a floating point comparison.
createFPCmp(SelectionDAG & DAG,const SDValue & Op)529 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
530 // must be a SETCC node
531 if (Op.getOpcode() != ISD::SETCC)
532 return Op;
533
534 SDValue LHS = Op.getOperand(0);
535
536 if (!LHS.getValueType().isFloatingPoint())
537 return Op;
538
539 SDValue RHS = Op.getOperand(1);
540 SDLoc DL(Op);
541
542 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
543 // node if necessary.
544 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
545
546 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
547 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
548 }
549
550 // Creates and returns a CMovFPT/F node.
createCMovFP(SelectionDAG & DAG,SDValue Cond,SDValue True,SDValue False,SDLoc DL)551 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
552 SDValue False, SDLoc DL) {
553 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
554 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
555 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
556
557 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
558 True.getValueType(), True, FCC0, False, Cond);
559 }
560
performSELECTCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)561 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
562 TargetLowering::DAGCombinerInfo &DCI,
563 const MipsSubtarget &Subtarget) {
564 if (DCI.isBeforeLegalizeOps())
565 return SDValue();
566
567 SDValue SetCC = N->getOperand(0);
568
569 if ((SetCC.getOpcode() != ISD::SETCC) ||
570 !SetCC.getOperand(0).getValueType().isInteger())
571 return SDValue();
572
573 SDValue False = N->getOperand(2);
574 EVT FalseTy = False.getValueType();
575
576 if (!FalseTy.isInteger())
577 return SDValue();
578
579 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
580
581 // If the RHS (False) is 0, we swap the order of the operands
582 // of ISD::SELECT (obviously also inverting the condition) so that we can
583 // take advantage of conditional moves using the $0 register.
584 // Example:
585 // return (a != 0) ? x : 0;
586 // load $reg, x
587 // movz $reg, $0, a
588 if (!FalseC)
589 return SDValue();
590
591 const SDLoc DL(N);
592
593 if (!FalseC->getZExtValue()) {
594 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
595 SDValue True = N->getOperand(1);
596
597 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
598 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
599
600 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
601 }
602
603 // If both operands are integer constants there's a possibility that we
604 // can do some interesting optimizations.
605 SDValue True = N->getOperand(1);
606 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
607
608 if (!TrueC || !True.getValueType().isInteger())
609 return SDValue();
610
611 // We'll also ignore MVT::i64 operands as this optimizations proves
612 // to be ineffective because of the required sign extensions as the result
613 // of a SETCC operator is always MVT::i32 for non-vector types.
614 if (True.getValueType() == MVT::i64)
615 return SDValue();
616
617 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
618
619 // 1) (a < x) ? y : y-1
620 // slti $reg1, a, x
621 // addiu $reg2, $reg1, y-1
622 if (Diff == 1)
623 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
624
625 // 2) (a < x) ? y-1 : y
626 // slti $reg1, a, x
627 // xor $reg1, $reg1, 1
628 // addiu $reg2, $reg1, y-1
629 if (Diff == -1) {
630 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
631 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
632 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
633 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
634 }
635
636 // Couldn't optimize.
637 return SDValue();
638 }
639
performCMovFPCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)640 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
641 TargetLowering::DAGCombinerInfo &DCI,
642 const MipsSubtarget &Subtarget) {
643 if (DCI.isBeforeLegalizeOps())
644 return SDValue();
645
646 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
647
648 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
649 if (!FalseC || FalseC->getZExtValue())
650 return SDValue();
651
652 // Since RHS (False) is 0, we swap the order of the True/False operands
653 // (obviously also inverting the condition) so that we can
654 // take advantage of conditional moves using the $0 register.
655 // Example:
656 // return (a != 0) ? x : 0;
657 // load $reg, x
658 // movz $reg, $0, a
659 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
660 MipsISD::CMovFP_T;
661
662 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
663 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
664 ValueIfFalse, FCC, ValueIfTrue, Glue);
665 }
666
performANDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)667 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
668 TargetLowering::DAGCombinerInfo &DCI,
669 const MipsSubtarget &Subtarget) {
670 // Pattern match EXT.
671 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
672 // => ext $dst, $src, size, pos
673 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
674 return SDValue();
675
676 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
677 unsigned ShiftRightOpc = ShiftRight.getOpcode();
678
679 // Op's first operand must be a shift right.
680 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
681 return SDValue();
682
683 // The second operand of the shift must be an immediate.
684 ConstantSDNode *CN;
685 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
686 return SDValue();
687
688 uint64_t Pos = CN->getZExtValue();
689 uint64_t SMPos, SMSize;
690
691 // Op's second operand must be a shifted mask.
692 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
693 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
694 return SDValue();
695
696 // Return if the shifted mask does not start at bit 0 or the sum of its size
697 // and Pos exceeds the word's size.
698 EVT ValTy = N->getValueType(0);
699 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
700 return SDValue();
701
702 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
703 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
704 DAG.getConstant(SMSize, MVT::i32));
705 }
706
performORCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)707 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
708 TargetLowering::DAGCombinerInfo &DCI,
709 const MipsSubtarget &Subtarget) {
710 // Pattern match INS.
711 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
712 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
713 // => ins $dst, $src, size, pos, $src1
714 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
715 return SDValue();
716
717 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
718 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
719 ConstantSDNode *CN;
720
721 // See if Op's first operand matches (and $src1 , mask0).
722 if (And0.getOpcode() != ISD::AND)
723 return SDValue();
724
725 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
726 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
727 return SDValue();
728
729 // See if Op's second operand matches (and (shl $src, pos), mask1).
730 if (And1.getOpcode() != ISD::AND)
731 return SDValue();
732
733 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
734 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
735 return SDValue();
736
737 // The shift masks must have the same position and size.
738 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
739 return SDValue();
740
741 SDValue Shl = And1.getOperand(0);
742 if (Shl.getOpcode() != ISD::SHL)
743 return SDValue();
744
745 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
746 return SDValue();
747
748 unsigned Shamt = CN->getZExtValue();
749
750 // Return if the shift amount and the first bit position of mask are not the
751 // same.
752 EVT ValTy = N->getValueType(0);
753 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
754 return SDValue();
755
756 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
757 DAG.getConstant(SMPos0, MVT::i32),
758 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
759 }
760
performADDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)761 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
762 TargetLowering::DAGCombinerInfo &DCI,
763 const MipsSubtarget &Subtarget) {
764 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
765
766 if (DCI.isBeforeLegalizeOps())
767 return SDValue();
768
769 SDValue Add = N->getOperand(1);
770
771 if (Add.getOpcode() != ISD::ADD)
772 return SDValue();
773
774 SDValue Lo = Add.getOperand(1);
775
776 if ((Lo.getOpcode() != MipsISD::Lo) ||
777 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
778 return SDValue();
779
780 EVT ValTy = N->getValueType(0);
781 SDLoc DL(N);
782
783 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
784 Add.getOperand(0));
785 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
786 }
787
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const788 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
789 const {
790 SelectionDAG &DAG = DCI.DAG;
791 unsigned Opc = N->getOpcode();
792
793 switch (Opc) {
794 default: break;
795 case ISD::SDIVREM:
796 case ISD::UDIVREM:
797 return performDivRemCombine(N, DAG, DCI, Subtarget);
798 case ISD::SELECT:
799 return performSELECTCombine(N, DAG, DCI, Subtarget);
800 case MipsISD::CMovFP_F:
801 case MipsISD::CMovFP_T:
802 return performCMovFPCombine(N, DAG, DCI, Subtarget);
803 case ISD::AND:
804 return performANDCombine(N, DAG, DCI, Subtarget);
805 case ISD::OR:
806 return performORCombine(N, DAG, DCI, Subtarget);
807 case ISD::ADD:
808 return performADDCombine(N, DAG, DCI, Subtarget);
809 }
810
811 return SDValue();
812 }
813
814 void
LowerOperationWrapper(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const815 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
816 SmallVectorImpl<SDValue> &Results,
817 SelectionDAG &DAG) const {
818 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
819
820 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
821 Results.push_back(Res.getValue(I));
822 }
823
824 void
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const825 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
826 SmallVectorImpl<SDValue> &Results,
827 SelectionDAG &DAG) const {
828 return LowerOperationWrapper(N, Results, DAG);
829 }
830
831 SDValue MipsTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const832 LowerOperation(SDValue Op, SelectionDAG &DAG) const
833 {
834 switch (Op.getOpcode())
835 {
836 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
837 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
838 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
839 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
840 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
841 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
842 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
843 case ISD::SELECT: return lowerSELECT(Op, DAG);
844 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
845 case ISD::SETCC: return lowerSETCC(Op, DAG);
846 case ISD::VASTART: return lowerVASTART(Op, DAG);
847 case ISD::VAARG: return lowerVAARG(Op, DAG);
848 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
849 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
850 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
851 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
852 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
853 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
854 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
855 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
856 case ISD::LOAD: return lowerLOAD(Op, DAG);
857 case ISD::STORE: return lowerSTORE(Op, DAG);
858 case ISD::ADD: return lowerADD(Op, DAG);
859 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
860 }
861 return SDValue();
862 }
863
864 //===----------------------------------------------------------------------===//
865 // Lower helper functions
866 //===----------------------------------------------------------------------===//
867
868 // addLiveIn - This helper function adds the specified physical register to the
869 // MachineFunction as a live in value. It also creates a corresponding
870 // virtual register for it.
871 static unsigned
addLiveIn(MachineFunction & MF,unsigned PReg,const TargetRegisterClass * RC)872 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
873 {
874 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
875 MF.getRegInfo().addLiveIn(PReg, VReg);
876 return VReg;
877 }
878
insertDivByZeroTrap(MachineInstr * MI,MachineBasicBlock & MBB,const TargetInstrInfo & TII,bool Is64Bit)879 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
880 MachineBasicBlock &MBB,
881 const TargetInstrInfo &TII,
882 bool Is64Bit) {
883 if (NoZeroDivCheck)
884 return &MBB;
885
886 // Insert instruction "teq $divisor_reg, $zero, 7".
887 MachineBasicBlock::iterator I(MI);
888 MachineInstrBuilder MIB;
889 MachineOperand &Divisor = MI->getOperand(2);
890 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
891 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
892 .addReg(Mips::ZERO).addImm(7);
893
894 // Use the 32-bit sub-register if this is a 64-bit division.
895 if (Is64Bit)
896 MIB->getOperand(0).setSubReg(Mips::sub_32);
897
898 // Clear Divisor's kill flag.
899 Divisor.setIsKill(false);
900
901 // We would normally delete the original instruction here but in this case
902 // we only needed to inject an additional instruction rather than replace it.
903
904 return &MBB;
905 }
906
907 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const908 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
909 MachineBasicBlock *BB) const {
910 switch (MI->getOpcode()) {
911 default:
912 llvm_unreachable("Unexpected instr type to insert");
913 case Mips::ATOMIC_LOAD_ADD_I8:
914 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
915 case Mips::ATOMIC_LOAD_ADD_I16:
916 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
917 case Mips::ATOMIC_LOAD_ADD_I32:
918 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
919 case Mips::ATOMIC_LOAD_ADD_I64:
920 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
921
922 case Mips::ATOMIC_LOAD_AND_I8:
923 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
924 case Mips::ATOMIC_LOAD_AND_I16:
925 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
926 case Mips::ATOMIC_LOAD_AND_I32:
927 return emitAtomicBinary(MI, BB, 4, Mips::AND);
928 case Mips::ATOMIC_LOAD_AND_I64:
929 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
930
931 case Mips::ATOMIC_LOAD_OR_I8:
932 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
933 case Mips::ATOMIC_LOAD_OR_I16:
934 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
935 case Mips::ATOMIC_LOAD_OR_I32:
936 return emitAtomicBinary(MI, BB, 4, Mips::OR);
937 case Mips::ATOMIC_LOAD_OR_I64:
938 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
939
940 case Mips::ATOMIC_LOAD_XOR_I8:
941 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
942 case Mips::ATOMIC_LOAD_XOR_I16:
943 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
944 case Mips::ATOMIC_LOAD_XOR_I32:
945 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
946 case Mips::ATOMIC_LOAD_XOR_I64:
947 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
948
949 case Mips::ATOMIC_LOAD_NAND_I8:
950 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
951 case Mips::ATOMIC_LOAD_NAND_I16:
952 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
953 case Mips::ATOMIC_LOAD_NAND_I32:
954 return emitAtomicBinary(MI, BB, 4, 0, true);
955 case Mips::ATOMIC_LOAD_NAND_I64:
956 return emitAtomicBinary(MI, BB, 8, 0, true);
957
958 case Mips::ATOMIC_LOAD_SUB_I8:
959 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
960 case Mips::ATOMIC_LOAD_SUB_I16:
961 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
962 case Mips::ATOMIC_LOAD_SUB_I32:
963 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
964 case Mips::ATOMIC_LOAD_SUB_I64:
965 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
966
967 case Mips::ATOMIC_SWAP_I8:
968 return emitAtomicBinaryPartword(MI, BB, 1, 0);
969 case Mips::ATOMIC_SWAP_I16:
970 return emitAtomicBinaryPartword(MI, BB, 2, 0);
971 case Mips::ATOMIC_SWAP_I32:
972 return emitAtomicBinary(MI, BB, 4, 0);
973 case Mips::ATOMIC_SWAP_I64:
974 return emitAtomicBinary(MI, BB, 8, 0);
975
976 case Mips::ATOMIC_CMP_SWAP_I8:
977 return emitAtomicCmpSwapPartword(MI, BB, 1);
978 case Mips::ATOMIC_CMP_SWAP_I16:
979 return emitAtomicCmpSwapPartword(MI, BB, 2);
980 case Mips::ATOMIC_CMP_SWAP_I32:
981 return emitAtomicCmpSwap(MI, BB, 4);
982 case Mips::ATOMIC_CMP_SWAP_I64:
983 return emitAtomicCmpSwap(MI, BB, 8);
984 case Mips::PseudoSDIV:
985 case Mips::PseudoUDIV:
986 case Mips::DIV:
987 case Mips::DIVU:
988 case Mips::MOD:
989 case Mips::MODU:
990 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false);
991 case Mips::PseudoDSDIV:
992 case Mips::PseudoDUDIV:
993 case Mips::DDIV:
994 case Mips::DDIVU:
995 case Mips::DMOD:
996 case Mips::DMODU:
997 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);
998 case Mips::SEL_D:
999 return emitSEL_D(MI, BB);
1000
1001 case Mips::PseudoSELECT_I:
1002 case Mips::PseudoSELECT_I64:
1003 case Mips::PseudoSELECT_S:
1004 case Mips::PseudoSELECT_D32:
1005 case Mips::PseudoSELECT_D64:
1006 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1007 case Mips::PseudoSELECTFP_F_I:
1008 case Mips::PseudoSELECTFP_F_I64:
1009 case Mips::PseudoSELECTFP_F_S:
1010 case Mips::PseudoSELECTFP_F_D32:
1011 case Mips::PseudoSELECTFP_F_D64:
1012 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1013 case Mips::PseudoSELECTFP_T_I:
1014 case Mips::PseudoSELECTFP_T_I64:
1015 case Mips::PseudoSELECTFP_T_S:
1016 case Mips::PseudoSELECTFP_T_D32:
1017 case Mips::PseudoSELECTFP_T_D64:
1018 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1019 }
1020 }
1021
1022 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1023 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1024 MachineBasicBlock *
emitAtomicBinary(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1025 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1026 unsigned Size, unsigned BinOpcode,
1027 bool Nand) const {
1028 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1029
1030 MachineFunction *MF = BB->getParent();
1031 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1032 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1033 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1034 DebugLoc DL = MI->getDebugLoc();
1035 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1036
1037 if (Size == 4) {
1038 if (isMicroMips) {
1039 LL = Mips::LL_MM;
1040 SC = Mips::SC_MM;
1041 } else {
1042 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1043 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1044 }
1045 AND = Mips::AND;
1046 NOR = Mips::NOR;
1047 ZERO = Mips::ZERO;
1048 BEQ = Mips::BEQ;
1049 } else {
1050 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1051 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1052 AND = Mips::AND64;
1053 NOR = Mips::NOR64;
1054 ZERO = Mips::ZERO_64;
1055 BEQ = Mips::BEQ64;
1056 }
1057
1058 unsigned OldVal = MI->getOperand(0).getReg();
1059 unsigned Ptr = MI->getOperand(1).getReg();
1060 unsigned Incr = MI->getOperand(2).getReg();
1061
1062 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1063 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1064 unsigned Success = RegInfo.createVirtualRegister(RC);
1065
1066 // insert new blocks after the current block
1067 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1068 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1069 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1070 MachineFunction::iterator It = BB;
1071 ++It;
1072 MF->insert(It, loopMBB);
1073 MF->insert(It, exitMBB);
1074
1075 // Transfer the remainder of BB and its successor edges to exitMBB.
1076 exitMBB->splice(exitMBB->begin(), BB,
1077 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1078 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1079
1080 // thisMBB:
1081 // ...
1082 // fallthrough --> loopMBB
1083 BB->addSuccessor(loopMBB);
1084 loopMBB->addSuccessor(loopMBB);
1085 loopMBB->addSuccessor(exitMBB);
1086
1087 // loopMBB:
1088 // ll oldval, 0(ptr)
1089 // <binop> storeval, oldval, incr
1090 // sc success, storeval, 0(ptr)
1091 // beq success, $0, loopMBB
1092 BB = loopMBB;
1093 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1094 if (Nand) {
1095 // and andres, oldval, incr
1096 // nor storeval, $0, andres
1097 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1098 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1099 } else if (BinOpcode) {
1100 // <binop> storeval, oldval, incr
1101 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1102 } else {
1103 StoreVal = Incr;
1104 }
1105 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1106 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1107
1108 MI->eraseFromParent(); // The instruction is gone now.
1109
1110 return exitMBB;
1111 }
1112
emitSignExtendToI32InReg(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned DstReg,unsigned SrcReg) const1113 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1114 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1115 unsigned SrcReg) const {
1116 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1117 DebugLoc DL = MI->getDebugLoc();
1118
1119 if (Subtarget.hasMips32r2() && Size == 1) {
1120 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1121 return BB;
1122 }
1123
1124 if (Subtarget.hasMips32r2() && Size == 2) {
1125 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1126 return BB;
1127 }
1128
1129 MachineFunction *MF = BB->getParent();
1130 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1131 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1132 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1133
1134 assert(Size < 32);
1135 int64_t ShiftImm = 32 - (Size * 8);
1136
1137 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1138 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1139
1140 return BB;
1141 }
1142
emitAtomicBinaryPartword(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1143 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1144 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1145 bool Nand) const {
1146 assert((Size == 1 || Size == 2) &&
1147 "Unsupported size for EmitAtomicBinaryPartial.");
1148
1149 MachineFunction *MF = BB->getParent();
1150 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1151 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1152 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1153 DebugLoc DL = MI->getDebugLoc();
1154
1155 unsigned Dest = MI->getOperand(0).getReg();
1156 unsigned Ptr = MI->getOperand(1).getReg();
1157 unsigned Incr = MI->getOperand(2).getReg();
1158
1159 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1160 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1161 unsigned Mask = RegInfo.createVirtualRegister(RC);
1162 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1163 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1164 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1165 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1166 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1167 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1168 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1169 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1170 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1171 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1172 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1173 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1174 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1175 unsigned Success = RegInfo.createVirtualRegister(RC);
1176
1177 // insert new blocks after the current block
1178 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1179 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1180 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1181 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1182 MachineFunction::iterator It = BB;
1183 ++It;
1184 MF->insert(It, loopMBB);
1185 MF->insert(It, sinkMBB);
1186 MF->insert(It, exitMBB);
1187
1188 // Transfer the remainder of BB and its successor edges to exitMBB.
1189 exitMBB->splice(exitMBB->begin(), BB,
1190 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1191 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1192
1193 BB->addSuccessor(loopMBB);
1194 loopMBB->addSuccessor(loopMBB);
1195 loopMBB->addSuccessor(sinkMBB);
1196 sinkMBB->addSuccessor(exitMBB);
1197
1198 // thisMBB:
1199 // addiu masklsb2,$0,-4 # 0xfffffffc
1200 // and alignedaddr,ptr,masklsb2
1201 // andi ptrlsb2,ptr,3
1202 // sll shiftamt,ptrlsb2,3
1203 // ori maskupper,$0,255 # 0xff
1204 // sll mask,maskupper,shiftamt
1205 // nor mask2,$0,mask
1206 // sll incr2,incr,shiftamt
1207
1208 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1209 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1210 .addReg(Mips::ZERO).addImm(-4);
1211 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1212 .addReg(Ptr).addReg(MaskLSB2);
1213 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1214 if (Subtarget.isLittle()) {
1215 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1216 } else {
1217 unsigned Off = RegInfo.createVirtualRegister(RC);
1218 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1219 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1220 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1221 }
1222 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1223 .addReg(Mips::ZERO).addImm(MaskImm);
1224 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1225 .addReg(MaskUpper).addReg(ShiftAmt);
1226 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1227 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1228
1229 // atomic.load.binop
1230 // loopMBB:
1231 // ll oldval,0(alignedaddr)
1232 // binop binopres,oldval,incr2
1233 // and newval,binopres,mask
1234 // and maskedoldval0,oldval,mask2
1235 // or storeval,maskedoldval0,newval
1236 // sc success,storeval,0(alignedaddr)
1237 // beq success,$0,loopMBB
1238
1239 // atomic.swap
1240 // loopMBB:
1241 // ll oldval,0(alignedaddr)
1242 // and newval,incr2,mask
1243 // and maskedoldval0,oldval,mask2
1244 // or storeval,maskedoldval0,newval
1245 // sc success,storeval,0(alignedaddr)
1246 // beq success,$0,loopMBB
1247
1248 BB = loopMBB;
1249 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1250 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1251 if (Nand) {
1252 // and andres, oldval, incr2
1253 // nor binopres, $0, andres
1254 // and newval, binopres, mask
1255 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1256 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1257 .addReg(Mips::ZERO).addReg(AndRes);
1258 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1259 } else if (BinOpcode) {
1260 // <binop> binopres, oldval, incr2
1261 // and newval, binopres, mask
1262 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1263 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1264 } else { // atomic.swap
1265 // and newval, incr2, mask
1266 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1267 }
1268
1269 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1270 .addReg(OldVal).addReg(Mask2);
1271 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1272 .addReg(MaskedOldVal0).addReg(NewVal);
1273 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1274 BuildMI(BB, DL, TII->get(SC), Success)
1275 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1276 BuildMI(BB, DL, TII->get(Mips::BEQ))
1277 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1278
1279 // sinkMBB:
1280 // and maskedoldval1,oldval,mask
1281 // srl srlres,maskedoldval1,shiftamt
1282 // sign_extend dest,srlres
1283 BB = sinkMBB;
1284
1285 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1286 .addReg(OldVal).addReg(Mask);
1287 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1288 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1289 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1290
1291 MI->eraseFromParent(); // The instruction is gone now.
1292
1293 return exitMBB;
1294 }
1295
emitAtomicCmpSwap(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size) const1296 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1297 MachineBasicBlock *BB,
1298 unsigned Size) const {
1299 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1300
1301 MachineFunction *MF = BB->getParent();
1302 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1303 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1304 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1305 DebugLoc DL = MI->getDebugLoc();
1306 unsigned LL, SC, ZERO, BNE, BEQ;
1307
1308 if (Size == 4) {
1309 LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1310 SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1311 ZERO = Mips::ZERO;
1312 BNE = Mips::BNE;
1313 BEQ = Mips::BEQ;
1314 } else {
1315 LL = Mips::LLD;
1316 SC = Mips::SCD;
1317 ZERO = Mips::ZERO_64;
1318 BNE = Mips::BNE64;
1319 BEQ = Mips::BEQ64;
1320 }
1321
1322 unsigned Dest = MI->getOperand(0).getReg();
1323 unsigned Ptr = MI->getOperand(1).getReg();
1324 unsigned OldVal = MI->getOperand(2).getReg();
1325 unsigned NewVal = MI->getOperand(3).getReg();
1326
1327 unsigned Success = RegInfo.createVirtualRegister(RC);
1328
1329 // insert new blocks after the current block
1330 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1331 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1332 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1333 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1334 MachineFunction::iterator It = BB;
1335 ++It;
1336 MF->insert(It, loop1MBB);
1337 MF->insert(It, loop2MBB);
1338 MF->insert(It, exitMBB);
1339
1340 // Transfer the remainder of BB and its successor edges to exitMBB.
1341 exitMBB->splice(exitMBB->begin(), BB,
1342 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1343 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1344
1345 // thisMBB:
1346 // ...
1347 // fallthrough --> loop1MBB
1348 BB->addSuccessor(loop1MBB);
1349 loop1MBB->addSuccessor(exitMBB);
1350 loop1MBB->addSuccessor(loop2MBB);
1351 loop2MBB->addSuccessor(loop1MBB);
1352 loop2MBB->addSuccessor(exitMBB);
1353
1354 // loop1MBB:
1355 // ll dest, 0(ptr)
1356 // bne dest, oldval, exitMBB
1357 BB = loop1MBB;
1358 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1359 BuildMI(BB, DL, TII->get(BNE))
1360 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1361
1362 // loop2MBB:
1363 // sc success, newval, 0(ptr)
1364 // beq success, $0, loop1MBB
1365 BB = loop2MBB;
1366 BuildMI(BB, DL, TII->get(SC), Success)
1367 .addReg(NewVal).addReg(Ptr).addImm(0);
1368 BuildMI(BB, DL, TII->get(BEQ))
1369 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1370
1371 MI->eraseFromParent(); // The instruction is gone now.
1372
1373 return exitMBB;
1374 }
1375
1376 MachineBasicBlock *
emitAtomicCmpSwapPartword(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size) const1377 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1378 MachineBasicBlock *BB,
1379 unsigned Size) const {
1380 assert((Size == 1 || Size == 2) &&
1381 "Unsupported size for EmitAtomicCmpSwapPartial.");
1382
1383 MachineFunction *MF = BB->getParent();
1384 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1385 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1386 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1387 DebugLoc DL = MI->getDebugLoc();
1388
1389 unsigned Dest = MI->getOperand(0).getReg();
1390 unsigned Ptr = MI->getOperand(1).getReg();
1391 unsigned CmpVal = MI->getOperand(2).getReg();
1392 unsigned NewVal = MI->getOperand(3).getReg();
1393
1394 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1395 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1396 unsigned Mask = RegInfo.createVirtualRegister(RC);
1397 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1398 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1399 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1400 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1401 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1402 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1403 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1404 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1405 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1406 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1407 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1408 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1409 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1410 unsigned Success = RegInfo.createVirtualRegister(RC);
1411
1412 // insert new blocks after the current block
1413 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1414 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1415 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1416 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1417 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1418 MachineFunction::iterator It = BB;
1419 ++It;
1420 MF->insert(It, loop1MBB);
1421 MF->insert(It, loop2MBB);
1422 MF->insert(It, sinkMBB);
1423 MF->insert(It, exitMBB);
1424
1425 // Transfer the remainder of BB and its successor edges to exitMBB.
1426 exitMBB->splice(exitMBB->begin(), BB,
1427 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1428 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1429
1430 BB->addSuccessor(loop1MBB);
1431 loop1MBB->addSuccessor(sinkMBB);
1432 loop1MBB->addSuccessor(loop2MBB);
1433 loop2MBB->addSuccessor(loop1MBB);
1434 loop2MBB->addSuccessor(sinkMBB);
1435 sinkMBB->addSuccessor(exitMBB);
1436
1437 // FIXME: computation of newval2 can be moved to loop2MBB.
1438 // thisMBB:
1439 // addiu masklsb2,$0,-4 # 0xfffffffc
1440 // and alignedaddr,ptr,masklsb2
1441 // andi ptrlsb2,ptr,3
1442 // sll shiftamt,ptrlsb2,3
1443 // ori maskupper,$0,255 # 0xff
1444 // sll mask,maskupper,shiftamt
1445 // nor mask2,$0,mask
1446 // andi maskedcmpval,cmpval,255
1447 // sll shiftedcmpval,maskedcmpval,shiftamt
1448 // andi maskednewval,newval,255
1449 // sll shiftednewval,maskednewval,shiftamt
1450 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1451 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1452 .addReg(Mips::ZERO).addImm(-4);
1453 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1454 .addReg(Ptr).addReg(MaskLSB2);
1455 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1456 if (Subtarget.isLittle()) {
1457 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1458 } else {
1459 unsigned Off = RegInfo.createVirtualRegister(RC);
1460 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1461 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1462 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1463 }
1464 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1465 .addReg(Mips::ZERO).addImm(MaskImm);
1466 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1467 .addReg(MaskUpper).addReg(ShiftAmt);
1468 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1469 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1470 .addReg(CmpVal).addImm(MaskImm);
1471 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1472 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1473 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1474 .addReg(NewVal).addImm(MaskImm);
1475 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1476 .addReg(MaskedNewVal).addReg(ShiftAmt);
1477
1478 // loop1MBB:
1479 // ll oldval,0(alginedaddr)
1480 // and maskedoldval0,oldval,mask
1481 // bne maskedoldval0,shiftedcmpval,sinkMBB
1482 BB = loop1MBB;
1483 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1484 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1485 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1486 .addReg(OldVal).addReg(Mask);
1487 BuildMI(BB, DL, TII->get(Mips::BNE))
1488 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1489
1490 // loop2MBB:
1491 // and maskedoldval1,oldval,mask2
1492 // or storeval,maskedoldval1,shiftednewval
1493 // sc success,storeval,0(alignedaddr)
1494 // beq success,$0,loop1MBB
1495 BB = loop2MBB;
1496 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1497 .addReg(OldVal).addReg(Mask2);
1498 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1499 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1500 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1501 BuildMI(BB, DL, TII->get(SC), Success)
1502 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1503 BuildMI(BB, DL, TII->get(Mips::BEQ))
1504 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1505
1506 // sinkMBB:
1507 // srl srlres,maskedoldval0,shiftamt
1508 // sign_extend dest,srlres
1509 BB = sinkMBB;
1510
1511 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1512 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1513 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1514
1515 MI->eraseFromParent(); // The instruction is gone now.
1516
1517 return exitMBB;
1518 }
1519
emitSEL_D(MachineInstr * MI,MachineBasicBlock * BB) const1520 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
1521 MachineBasicBlock *BB) const {
1522 MachineFunction *MF = BB->getParent();
1523 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1524 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1525 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1526 DebugLoc DL = MI->getDebugLoc();
1527 MachineBasicBlock::iterator II(MI);
1528
1529 unsigned Fc = MI->getOperand(1).getReg();
1530 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1531
1532 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1533
1534 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1535 .addImm(0)
1536 .addReg(Fc)
1537 .addImm(Mips::sub_lo);
1538
1539 // We don't erase the original instruction, we just replace the condition
1540 // register with the 64-bit super-register.
1541 MI->getOperand(1).setReg(Fc2);
1542
1543 return BB;
1544 }
1545
1546 //===----------------------------------------------------------------------===//
1547 // Misc Lower Operation implementation
1548 //===----------------------------------------------------------------------===//
lowerBR_JT(SDValue Op,SelectionDAG & DAG) const1549 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1550 SDValue Chain = Op.getOperand(0);
1551 SDValue Table = Op.getOperand(1);
1552 SDValue Index = Op.getOperand(2);
1553 SDLoc DL(Op);
1554 EVT PTy = getPointerTy();
1555 unsigned EntrySize =
1556 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1557
1558 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1559 DAG.getConstant(EntrySize, PTy));
1560 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1561
1562 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1563 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1564 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1565 false, 0);
1566 Chain = Addr.getValue(1);
1567
1568 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || ABI.IsN64()) {
1569 // For PIC, the sequence is:
1570 // BRIND(load(Jumptable + index) + RelocBase)
1571 // RelocBase can be JumpTable, GOT or some sort of global base.
1572 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1573 getPICJumpTableRelocBase(Table, DAG));
1574 }
1575
1576 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1577 }
1578
lowerBRCOND(SDValue Op,SelectionDAG & DAG) const1579 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1580 // The first operand is the chain, the second is the condition, the third is
1581 // the block to branch to if the condition is true.
1582 SDValue Chain = Op.getOperand(0);
1583 SDValue Dest = Op.getOperand(2);
1584 SDLoc DL(Op);
1585
1586 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1587 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1588
1589 // Return if flag is not set by a floating point comparison.
1590 if (CondRes.getOpcode() != MipsISD::FPCmp)
1591 return Op;
1592
1593 SDValue CCNode = CondRes.getOperand(2);
1594 Mips::CondCode CC =
1595 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1596 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1597 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1598 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1599 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1600 FCC0, Dest, CondRes);
1601 }
1602
1603 SDValue MipsTargetLowering::
lowerSELECT(SDValue Op,SelectionDAG & DAG) const1604 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1605 {
1606 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1607 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1608
1609 // Return if flag is not set by a floating point comparison.
1610 if (Cond.getOpcode() != MipsISD::FPCmp)
1611 return Op;
1612
1613 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1614 SDLoc(Op));
1615 }
1616
1617 SDValue MipsTargetLowering::
lowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const1618 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1619 {
1620 SDLoc DL(Op);
1621 EVT Ty = Op.getOperand(0).getValueType();
1622 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1623 getSetCCResultType(*DAG.getContext(), Ty),
1624 Op.getOperand(0), Op.getOperand(1),
1625 Op.getOperand(4));
1626
1627 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1628 Op.getOperand(3));
1629 }
1630
lowerSETCC(SDValue Op,SelectionDAG & DAG) const1631 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1632 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1633 SDValue Cond = createFPCmp(DAG, Op);
1634
1635 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1636 "Floating point operand expected.");
1637
1638 SDValue True = DAG.getConstant(1, MVT::i32);
1639 SDValue False = DAG.getConstant(0, MVT::i32);
1640
1641 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1642 }
1643
lowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1644 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1645 SelectionDAG &DAG) const {
1646 EVT Ty = Op.getValueType();
1647 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1648 const GlobalValue *GV = N->getGlobal();
1649
1650 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1651 const MipsTargetObjectFile *TLOF =
1652 static_cast<const MipsTargetObjectFile *>(
1653 getTargetMachine().getObjFileLowering());
1654 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
1655 // %gp_rel relocation
1656 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1657
1658 // %hi/%lo relocation
1659 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1660 }
1661
1662 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1663 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1664
1665 if (LargeGOT)
1666 return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16,
1667 MipsII::MO_GOT_LO16, DAG.getEntryNode(),
1668 MachinePointerInfo::getGOT());
1669
1670 return getAddrGlobal(N, SDLoc(N), Ty, DAG,
1671 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP
1672 : MipsII::MO_GOT16,
1673 DAG.getEntryNode(), MachinePointerInfo::getGOT());
1674 }
1675
lowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1676 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1677 SelectionDAG &DAG) const {
1678 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1679 EVT Ty = Op.getValueType();
1680
1681 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1682 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1683
1684 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1685 }
1686
1687 SDValue MipsTargetLowering::
lowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1688 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1689 {
1690 // If the relocation model is PIC, use the General Dynamic TLS Model or
1691 // Local Dynamic TLS model, otherwise use the Initial Exec or
1692 // Local Exec TLS Model.
1693
1694 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1695 SDLoc DL(GA);
1696 const GlobalValue *GV = GA->getGlobal();
1697 EVT PtrVT = getPointerTy();
1698
1699 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1700
1701 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1702 // General Dynamic and Local Dynamic TLS Model.
1703 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1704 : MipsII::MO_TLSGD;
1705
1706 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1707 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1708 getGlobalReg(DAG, PtrVT), TGA);
1709 unsigned PtrSize = PtrVT.getSizeInBits();
1710 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1711
1712 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1713
1714 ArgListTy Args;
1715 ArgListEntry Entry;
1716 Entry.Node = Argument;
1717 Entry.Ty = PtrTy;
1718 Args.push_back(Entry);
1719
1720 TargetLowering::CallLoweringInfo CLI(DAG);
1721 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1722 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1723 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1724
1725 SDValue Ret = CallResult.first;
1726
1727 if (model != TLSModel::LocalDynamic)
1728 return Ret;
1729
1730 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1731 MipsII::MO_DTPREL_HI);
1732 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1733 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1734 MipsII::MO_DTPREL_LO);
1735 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1736 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1737 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1738 }
1739
1740 SDValue Offset;
1741 if (model == TLSModel::InitialExec) {
1742 // Initial Exec TLS Model
1743 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1744 MipsII::MO_GOTTPREL);
1745 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1746 TGA);
1747 Offset = DAG.getLoad(PtrVT, DL,
1748 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1749 false, false, false, 0);
1750 } else {
1751 // Local Exec TLS Model
1752 assert(model == TLSModel::LocalExec);
1753 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1754 MipsII::MO_TPREL_HI);
1755 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1756 MipsII::MO_TPREL_LO);
1757 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1758 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1759 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1760 }
1761
1762 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1763 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1764 }
1765
1766 SDValue MipsTargetLowering::
lowerJumpTable(SDValue Op,SelectionDAG & DAG) const1767 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1768 {
1769 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1770 EVT Ty = Op.getValueType();
1771
1772 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1773 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1774
1775 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1776 }
1777
1778 SDValue MipsTargetLowering::
lowerConstantPool(SDValue Op,SelectionDAG & DAG) const1779 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1780 {
1781 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1782 EVT Ty = Op.getValueType();
1783
1784 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1785 const MipsTargetObjectFile *TLOF =
1786 static_cast<const MipsTargetObjectFile *>(
1787 getTargetMachine().getObjFileLowering());
1788
1789 if (TLOF->IsConstantInSmallSection(N->getConstVal(), getTargetMachine()))
1790 // %gp_rel relocation
1791 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1792
1793 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1794 }
1795
1796 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1797 }
1798
lowerVASTART(SDValue Op,SelectionDAG & DAG) const1799 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1800 MachineFunction &MF = DAG.getMachineFunction();
1801 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1802
1803 SDLoc DL(Op);
1804 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1805 getPointerTy());
1806
1807 // vastart just stores the address of the VarArgsFrameIndex slot into the
1808 // memory location argument.
1809 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1810 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1811 MachinePointerInfo(SV), false, false, 0);
1812 }
1813
lowerVAARG(SDValue Op,SelectionDAG & DAG) const1814 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1815 SDNode *Node = Op.getNode();
1816 EVT VT = Node->getValueType(0);
1817 SDValue Chain = Node->getOperand(0);
1818 SDValue VAListPtr = Node->getOperand(1);
1819 unsigned Align = Node->getConstantOperandVal(3);
1820 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1821 SDLoc DL(Node);
1822 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
1823
1824 SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr,
1825 MachinePointerInfo(SV), false, false, false,
1826 0);
1827 SDValue VAList = VAListLoad;
1828
1829 // Re-align the pointer if necessary.
1830 // It should only ever be necessary for 64-bit types on O32 since the minimum
1831 // argument alignment is the same as the maximum type alignment for N32/N64.
1832 //
1833 // FIXME: We currently align too often. The code generator doesn't notice
1834 // when the pointer is still aligned from the last va_arg (or pair of
1835 // va_args for the i64 on O32 case).
1836 if (Align > getMinStackArgumentAlignment()) {
1837 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
1838
1839 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1840 DAG.getConstant(Align - 1,
1841 VAList.getValueType()));
1842
1843 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1844 DAG.getConstant(-(int64_t)Align,
1845 VAList.getValueType()));
1846 }
1847
1848 // Increment the pointer, VAList, to the next vaarg.
1849 unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1850 SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1851 DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
1852 VAList.getValueType()));
1853 // Store the incremented VAList to the legalized pointer
1854 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1855 MachinePointerInfo(SV), false, false, 0);
1856
1857 // In big-endian mode we must adjust the pointer when the load size is smaller
1858 // than the argument slot size. We must also reduce the known alignment to
1859 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1860 // the correct half of the slot, and reduce the alignment from 8 (slot
1861 // alignment) down to 4 (type alignment).
1862 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1863 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1864 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1865 DAG.getIntPtrConstant(Adjustment));
1866 }
1867 // Load the actual argument out of the pointer VAList
1868 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1869 false, 0);
1870 }
1871
lowerFCOPYSIGN32(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)1872 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1873 bool HasExtractInsert) {
1874 EVT TyX = Op.getOperand(0).getValueType();
1875 EVT TyY = Op.getOperand(1).getValueType();
1876 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1877 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1878 SDLoc DL(Op);
1879 SDValue Res;
1880
1881 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1882 // to i32.
1883 SDValue X = (TyX == MVT::f32) ?
1884 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1885 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1886 Const1);
1887 SDValue Y = (TyY == MVT::f32) ?
1888 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1889 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1890 Const1);
1891
1892 if (HasExtractInsert) {
1893 // ext E, Y, 31, 1 ; extract bit31 of Y
1894 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1895 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1896 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1897 } else {
1898 // sll SllX, X, 1
1899 // srl SrlX, SllX, 1
1900 // srl SrlY, Y, 31
1901 // sll SllY, SrlX, 31
1902 // or Or, SrlX, SllY
1903 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1904 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1905 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1906 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1907 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1908 }
1909
1910 if (TyX == MVT::f32)
1911 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1912
1913 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1914 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1915 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1916 }
1917
lowerFCOPYSIGN64(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)1918 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
1919 bool HasExtractInsert) {
1920 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1921 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1922 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1923 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1924 SDLoc DL(Op);
1925
1926 // Bitcast to integer nodes.
1927 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1928 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1929
1930 if (HasExtractInsert) {
1931 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1932 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1933 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1934 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1935
1936 if (WidthX > WidthY)
1937 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1938 else if (WidthY > WidthX)
1939 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1940
1941 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1942 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1943 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1944 }
1945
1946 // (d)sll SllX, X, 1
1947 // (d)srl SrlX, SllX, 1
1948 // (d)srl SrlY, Y, width(Y)-1
1949 // (d)sll SllY, SrlX, width(Y)-1
1950 // or Or, SrlX, SllY
1951 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1952 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1953 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1954 DAG.getConstant(WidthY - 1, MVT::i32));
1955
1956 if (WidthX > WidthY)
1957 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1958 else if (WidthY > WidthX)
1959 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1960
1961 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1962 DAG.getConstant(WidthX - 1, MVT::i32));
1963 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1964 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1965 }
1966
1967 SDValue
lowerFCOPYSIGN(SDValue Op,SelectionDAG & DAG) const1968 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1969 if (Subtarget.isGP64bit())
1970 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
1971
1972 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
1973 }
1974
1975 SDValue MipsTargetLowering::
lowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const1976 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1977 // check the depth
1978 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1979 "Frame address can only be determined for current frame.");
1980
1981 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1982 MFI->setFrameAddressIsTaken(true);
1983 EVT VT = Op.getValueType();
1984 SDLoc DL(Op);
1985 SDValue FrameAddr = DAG.getCopyFromReg(
1986 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
1987 return FrameAddr;
1988 }
1989
lowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const1990 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1991 SelectionDAG &DAG) const {
1992 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1993 return SDValue();
1994
1995 // check the depth
1996 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1997 "Return address can be determined only for current frame.");
1998
1999 MachineFunction &MF = DAG.getMachineFunction();
2000 MachineFrameInfo *MFI = MF.getFrameInfo();
2001 MVT VT = Op.getSimpleValueType();
2002 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2003 MFI->setReturnAddressIsTaken(true);
2004
2005 // Return RA, which contains the return address. Mark it an implicit live-in.
2006 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2007 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2008 }
2009
2010 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2011 // generated from __builtin_eh_return (offset, handler)
2012 // The effect of this is to adjust the stack pointer by "offset"
2013 // and then branch to "handler".
lowerEH_RETURN(SDValue Op,SelectionDAG & DAG) const2014 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2015 const {
2016 MachineFunction &MF = DAG.getMachineFunction();
2017 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2018
2019 MipsFI->setCallsEhReturn();
2020 SDValue Chain = Op.getOperand(0);
2021 SDValue Offset = Op.getOperand(1);
2022 SDValue Handler = Op.getOperand(2);
2023 SDLoc DL(Op);
2024 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2025
2026 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2027 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2028 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2029 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2030 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2031 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2032 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2033 DAG.getRegister(OffsetReg, Ty),
2034 DAG.getRegister(AddrReg, getPointerTy()),
2035 Chain.getValue(1));
2036 }
2037
lowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const2038 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2039 SelectionDAG &DAG) const {
2040 // FIXME: Need pseudo-fence for 'singlethread' fences
2041 // FIXME: Set SType for weaker fences where supported/appropriate.
2042 unsigned SType = 0;
2043 SDLoc DL(Op);
2044 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2045 DAG.getConstant(SType, MVT::i32));
2046 }
2047
lowerShiftLeftParts(SDValue Op,SelectionDAG & DAG) const2048 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2049 SelectionDAG &DAG) const {
2050 SDLoc DL(Op);
2051 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2052
2053 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2054 SDValue Shamt = Op.getOperand(2);
2055 // if shamt < (VT.bits):
2056 // lo = (shl lo, shamt)
2057 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2058 // else:
2059 // lo = 0
2060 // hi = (shl lo, shamt[4:0])
2061 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2062 DAG.getConstant(-1, MVT::i32));
2063 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2064 DAG.getConstant(1, VT));
2065 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2066 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2067 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2068 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2069 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2070 DAG.getConstant(0x20, MVT::i32));
2071 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2072 DAG.getConstant(0, VT), ShiftLeftLo);
2073 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2074
2075 SDValue Ops[2] = {Lo, Hi};
2076 return DAG.getMergeValues(Ops, DL);
2077 }
2078
lowerShiftRightParts(SDValue Op,SelectionDAG & DAG,bool IsSRA) const2079 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2080 bool IsSRA) const {
2081 SDLoc DL(Op);
2082 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2083 SDValue Shamt = Op.getOperand(2);
2084 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2085
2086 // if shamt < (VT.bits):
2087 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2088 // if isSRA:
2089 // hi = (sra hi, shamt)
2090 // else:
2091 // hi = (srl hi, shamt)
2092 // else:
2093 // if isSRA:
2094 // lo = (sra hi, shamt[4:0])
2095 // hi = (sra hi, 31)
2096 // else:
2097 // lo = (srl hi, shamt[4:0])
2098 // hi = 0
2099 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2100 DAG.getConstant(-1, MVT::i32));
2101 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2102 DAG.getConstant(1, VT));
2103 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2104 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2105 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2106 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2107 DL, VT, Hi, Shamt);
2108 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2109 DAG.getConstant(0x20, MVT::i32));
2110 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
2111 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2112 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2113 IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
2114
2115 SDValue Ops[2] = {Lo, Hi};
2116 return DAG.getMergeValues(Ops, DL);
2117 }
2118
createLoadLR(unsigned Opc,SelectionDAG & DAG,LoadSDNode * LD,SDValue Chain,SDValue Src,unsigned Offset)2119 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2120 SDValue Chain, SDValue Src, unsigned Offset) {
2121 SDValue Ptr = LD->getBasePtr();
2122 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2123 EVT BasePtrVT = Ptr.getValueType();
2124 SDLoc DL(LD);
2125 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2126
2127 if (Offset)
2128 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2129 DAG.getConstant(Offset, BasePtrVT));
2130
2131 SDValue Ops[] = { Chain, Ptr, Src };
2132 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2133 LD->getMemOperand());
2134 }
2135
2136 // Expand an unaligned 32 or 64-bit integer load node.
lowerLOAD(SDValue Op,SelectionDAG & DAG) const2137 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2138 LoadSDNode *LD = cast<LoadSDNode>(Op);
2139 EVT MemVT = LD->getMemoryVT();
2140
2141 if (Subtarget.systemSupportsUnalignedAccess())
2142 return Op;
2143
2144 // Return if load is aligned or if MemVT is neither i32 nor i64.
2145 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2146 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2147 return SDValue();
2148
2149 bool IsLittle = Subtarget.isLittle();
2150 EVT VT = Op.getValueType();
2151 ISD::LoadExtType ExtType = LD->getExtensionType();
2152 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2153
2154 assert((VT == MVT::i32) || (VT == MVT::i64));
2155
2156 // Expand
2157 // (set dst, (i64 (load baseptr)))
2158 // to
2159 // (set tmp, (ldl (add baseptr, 7), undef))
2160 // (set dst, (ldr baseptr, tmp))
2161 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2162 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2163 IsLittle ? 7 : 0);
2164 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2165 IsLittle ? 0 : 7);
2166 }
2167
2168 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2169 IsLittle ? 3 : 0);
2170 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2171 IsLittle ? 0 : 3);
2172
2173 // Expand
2174 // (set dst, (i32 (load baseptr))) or
2175 // (set dst, (i64 (sextload baseptr))) or
2176 // (set dst, (i64 (extload baseptr)))
2177 // to
2178 // (set tmp, (lwl (add baseptr, 3), undef))
2179 // (set dst, (lwr baseptr, tmp))
2180 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2181 (ExtType == ISD::EXTLOAD))
2182 return LWR;
2183
2184 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2185
2186 // Expand
2187 // (set dst, (i64 (zextload baseptr)))
2188 // to
2189 // (set tmp0, (lwl (add baseptr, 3), undef))
2190 // (set tmp1, (lwr baseptr, tmp0))
2191 // (set tmp2, (shl tmp1, 32))
2192 // (set dst, (srl tmp2, 32))
2193 SDLoc DL(LD);
2194 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2195 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2196 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2197 SDValue Ops[] = { SRL, LWR.getValue(1) };
2198 return DAG.getMergeValues(Ops, DL);
2199 }
2200
createStoreLR(unsigned Opc,SelectionDAG & DAG,StoreSDNode * SD,SDValue Chain,unsigned Offset)2201 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2202 SDValue Chain, unsigned Offset) {
2203 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2204 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2205 SDLoc DL(SD);
2206 SDVTList VTList = DAG.getVTList(MVT::Other);
2207
2208 if (Offset)
2209 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2210 DAG.getConstant(Offset, BasePtrVT));
2211
2212 SDValue Ops[] = { Chain, Value, Ptr };
2213 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2214 SD->getMemOperand());
2215 }
2216
2217 // Expand an unaligned 32 or 64-bit integer store node.
lowerUnalignedIntStore(StoreSDNode * SD,SelectionDAG & DAG,bool IsLittle)2218 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2219 bool IsLittle) {
2220 SDValue Value = SD->getValue(), Chain = SD->getChain();
2221 EVT VT = Value.getValueType();
2222
2223 // Expand
2224 // (store val, baseptr) or
2225 // (truncstore val, baseptr)
2226 // to
2227 // (swl val, (add baseptr, 3))
2228 // (swr val, baseptr)
2229 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2230 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2231 IsLittle ? 3 : 0);
2232 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2233 }
2234
2235 assert(VT == MVT::i64);
2236
2237 // Expand
2238 // (store val, baseptr)
2239 // to
2240 // (sdl val, (add baseptr, 7))
2241 // (sdr val, baseptr)
2242 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2243 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2244 }
2245
2246 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
lowerFP_TO_SINT_STORE(StoreSDNode * SD,SelectionDAG & DAG)2247 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2248 SDValue Val = SD->getValue();
2249
2250 if (Val.getOpcode() != ISD::FP_TO_SINT)
2251 return SDValue();
2252
2253 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2254 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2255 Val.getOperand(0));
2256
2257 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2258 SD->getPointerInfo(), SD->isVolatile(),
2259 SD->isNonTemporal(), SD->getAlignment());
2260 }
2261
lowerSTORE(SDValue Op,SelectionDAG & DAG) const2262 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2263 StoreSDNode *SD = cast<StoreSDNode>(Op);
2264 EVT MemVT = SD->getMemoryVT();
2265
2266 // Lower unaligned integer stores.
2267 if (!Subtarget.systemSupportsUnalignedAccess() &&
2268 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2269 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2270 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2271
2272 return lowerFP_TO_SINT_STORE(SD, DAG);
2273 }
2274
lowerADD(SDValue Op,SelectionDAG & DAG) const2275 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2276 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2277 || cast<ConstantSDNode>
2278 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2279 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2280 return SDValue();
2281
2282 // The pattern
2283 // (add (frameaddr 0), (frame_to_args_offset))
2284 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2285 // (add FrameObject, 0)
2286 // where FrameObject is a fixed StackObject with offset 0 which points to
2287 // the old stack pointer.
2288 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2289 EVT ValTy = Op->getValueType(0);
2290 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2291 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2292 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2293 DAG.getConstant(0, ValTy));
2294 }
2295
lowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG) const2296 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2297 SelectionDAG &DAG) const {
2298 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2299 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2300 Op.getOperand(0));
2301 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2302 }
2303
2304 //===----------------------------------------------------------------------===//
2305 // Calling Convention Implementation
2306 //===----------------------------------------------------------------------===//
2307
2308 //===----------------------------------------------------------------------===//
2309 // TODO: Implement a generic logic using tblgen that can support this.
2310 // Mips O32 ABI rules:
2311 // ---
2312 // i32 - Passed in A0, A1, A2, A3 and stack
2313 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2314 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2315 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2316 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2317 // not used, it must be shadowed. If only A3 is available, shadow it and
2318 // go to stack.
2319 //
2320 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2321 //===----------------------------------------------------------------------===//
2322
CC_MipsO32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State,ArrayRef<MCPhysReg> F64Regs)2323 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2324 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2325 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2326 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2327 State.getMachineFunction().getSubtarget());
2328
2329 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2330 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2331
2332 // Do not process byval args here.
2333 if (ArgFlags.isByVal())
2334 return true;
2335
2336 // Promote i8 and i16
2337 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2338 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2339 LocVT = MVT::i32;
2340 if (ArgFlags.isSExt())
2341 LocInfo = CCValAssign::SExtUpper;
2342 else if (ArgFlags.isZExt())
2343 LocInfo = CCValAssign::ZExtUpper;
2344 else
2345 LocInfo = CCValAssign::AExtUpper;
2346 }
2347 }
2348
2349 // Promote i8 and i16
2350 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2351 LocVT = MVT::i32;
2352 if (ArgFlags.isSExt())
2353 LocInfo = CCValAssign::SExt;
2354 else if (ArgFlags.isZExt())
2355 LocInfo = CCValAssign::ZExt;
2356 else
2357 LocInfo = CCValAssign::AExt;
2358 }
2359
2360 unsigned Reg;
2361
2362 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2363 // is true: function is vararg, argument is 3rd or higher, there is previous
2364 // argument which is not f32 or f64.
2365 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2366 State.getFirstUnallocated(F32Regs) != ValNo;
2367 unsigned OrigAlign = ArgFlags.getOrigAlign();
2368 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2369
2370 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2371 Reg = State.AllocateReg(IntRegs);
2372 // If this is the first part of an i64 arg,
2373 // the allocated register must be either A0 or A2.
2374 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2375 Reg = State.AllocateReg(IntRegs);
2376 LocVT = MVT::i32;
2377 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2378 // Allocate int register and shadow next int register. If first
2379 // available register is Mips::A1 or Mips::A3, shadow it too.
2380 Reg = State.AllocateReg(IntRegs);
2381 if (Reg == Mips::A1 || Reg == Mips::A3)
2382 Reg = State.AllocateReg(IntRegs);
2383 State.AllocateReg(IntRegs);
2384 LocVT = MVT::i32;
2385 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2386 // we are guaranteed to find an available float register
2387 if (ValVT == MVT::f32) {
2388 Reg = State.AllocateReg(F32Regs);
2389 // Shadow int register
2390 State.AllocateReg(IntRegs);
2391 } else {
2392 Reg = State.AllocateReg(F64Regs);
2393 // Shadow int registers
2394 unsigned Reg2 = State.AllocateReg(IntRegs);
2395 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2396 State.AllocateReg(IntRegs);
2397 State.AllocateReg(IntRegs);
2398 }
2399 } else
2400 llvm_unreachable("Cannot handle this ValVT.");
2401
2402 if (!Reg) {
2403 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2404 OrigAlign);
2405 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2406 } else
2407 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2408
2409 return false;
2410 }
2411
CC_MipsO32_FP32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2412 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2413 MVT LocVT, CCValAssign::LocInfo LocInfo,
2414 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2415 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2416
2417 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2418 }
2419
CC_MipsO32_FP64(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2420 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2421 MVT LocVT, CCValAssign::LocInfo LocInfo,
2422 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2423 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2424
2425 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2426 }
2427
2428 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2429 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2430 CCState &State) LLVM_ATTRIBUTE_UNUSED;
2431
2432 #include "MipsGenCallingConv.inc"
2433
2434 //===----------------------------------------------------------------------===//
2435 // Call Calling Convention Implementation
2436 //===----------------------------------------------------------------------===//
2437
2438 // Return next O32 integer argument register.
getNextIntArgReg(unsigned Reg)2439 static unsigned getNextIntArgReg(unsigned Reg) {
2440 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2441 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2442 }
2443
2444 SDValue
passArgOnStack(SDValue StackPtr,unsigned Offset,SDValue Chain,SDValue Arg,SDLoc DL,bool IsTailCall,SelectionDAG & DAG) const2445 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2446 SDValue Chain, SDValue Arg, SDLoc DL,
2447 bool IsTailCall, SelectionDAG &DAG) const {
2448 if (!IsTailCall) {
2449 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2450 DAG.getIntPtrConstant(Offset));
2451 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2452 false, 0);
2453 }
2454
2455 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2456 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2457 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2458 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2459 /*isVolatile=*/ true, false, 0);
2460 }
2461
2462 void MipsTargetLowering::
getOpndList(SmallVectorImpl<SDValue> & Ops,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,bool IsPICCall,bool GlobalOrExternal,bool InternalLinkage,bool IsCallReloc,CallLoweringInfo & CLI,SDValue Callee,SDValue Chain) const2463 getOpndList(SmallVectorImpl<SDValue> &Ops,
2464 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2465 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2466 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2467 SDValue Chain) const {
2468 // Insert node "GP copy globalreg" before call to function.
2469 //
2470 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2471 // in PIC mode) allow symbols to be resolved via lazy binding.
2472 // The lazy binding stub requires GP to point to the GOT.
2473 // Note that we don't need GP to point to the GOT for indirect calls
2474 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2475 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2476 // used for the function (that is, Mips linker doesn't generate lazy binding
2477 // stub for a function whose address is taken in the program).
2478 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2479 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2480 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2481 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2482 }
2483
2484 // Build a sequence of copy-to-reg nodes chained together with token
2485 // chain and flag operands which copy the outgoing args into registers.
2486 // The InFlag in necessary since all emitted instructions must be
2487 // stuck together.
2488 SDValue InFlag;
2489
2490 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2491 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2492 RegsToPass[i].second, InFlag);
2493 InFlag = Chain.getValue(1);
2494 }
2495
2496 // Add argument registers to the end of the list so that they are
2497 // known live into the call.
2498 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2499 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2500 RegsToPass[i].second.getValueType()));
2501
2502 // Add a register mask operand representing the call-preserved registers.
2503 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2504 const uint32_t *Mask =
2505 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2506 assert(Mask && "Missing call preserved mask for calling convention");
2507 if (Subtarget.inMips16HardFloat()) {
2508 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2509 llvm::StringRef Sym = G->getGlobal()->getName();
2510 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2511 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2512 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2513 }
2514 }
2515 }
2516 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2517
2518 if (InFlag.getNode())
2519 Ops.push_back(InFlag);
2520 }
2521
2522 /// LowerCall - functions arguments are copied from virtual regs to
2523 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2524 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const2525 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2526 SmallVectorImpl<SDValue> &InVals) const {
2527 SelectionDAG &DAG = CLI.DAG;
2528 SDLoc DL = CLI.DL;
2529 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2530 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2531 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2532 SDValue Chain = CLI.Chain;
2533 SDValue Callee = CLI.Callee;
2534 bool &IsTailCall = CLI.IsTailCall;
2535 CallingConv::ID CallConv = CLI.CallConv;
2536 bool IsVarArg = CLI.IsVarArg;
2537
2538 MachineFunction &MF = DAG.getMachineFunction();
2539 MachineFrameInfo *MFI = MF.getFrameInfo();
2540 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2541 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2542 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2543
2544 // Analyze operands of the call, assigning locations to each operand.
2545 SmallVector<CCValAssign, 16> ArgLocs;
2546 MipsCCState CCInfo(
2547 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2548 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2549
2550 // Allocate the reserved argument area. It seems strange to do this from the
2551 // caller side but removing it breaks the frame size calculation.
2552 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2553
2554 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2555
2556 // Get a count of how many bytes are to be pushed on the stack.
2557 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2558
2559 // Check if it's really possible to do a tail call.
2560 if (IsTailCall)
2561 IsTailCall = isEligibleForTailCallOptimization(
2562 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2563
2564 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2565 report_fatal_error("failed to perform tail call elimination on a call "
2566 "site marked musttail");
2567
2568 if (IsTailCall)
2569 ++NumTailCalls;
2570
2571 // Chain is the output chain of the last Load/Store or CopyToReg node.
2572 // ByValChain is the output chain of the last Memcpy node created for copying
2573 // byval arguments to the stack.
2574 unsigned StackAlignment = TFL->getStackAlignment();
2575 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2576 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2577
2578 if (!IsTailCall)
2579 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2580
2581 SDValue StackPtr = DAG.getCopyFromReg(
2582 Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, getPointerTy());
2583
2584 // With EABI is it possible to have 16 args on registers.
2585 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2586 SmallVector<SDValue, 8> MemOpChains;
2587
2588 CCInfo.rewindByValRegsInfo();
2589
2590 // Walk the register/memloc assignments, inserting copies/loads.
2591 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2592 SDValue Arg = OutVals[i];
2593 CCValAssign &VA = ArgLocs[i];
2594 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2595 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2596 bool UseUpperBits = false;
2597
2598 // ByVal Arg.
2599 if (Flags.isByVal()) {
2600 unsigned FirstByValReg, LastByValReg;
2601 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2602 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2603
2604 assert(Flags.getByValSize() &&
2605 "ByVal args of size 0 should have been ignored by front-end.");
2606 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2607 assert(!IsTailCall &&
2608 "Do not tail-call optimize if there is a byval argument.");
2609 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2610 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2611 VA);
2612 CCInfo.nextInRegsParam();
2613 continue;
2614 }
2615
2616 // Promote the value if needed.
2617 switch (VA.getLocInfo()) {
2618 default:
2619 llvm_unreachable("Unknown loc info!");
2620 case CCValAssign::Full:
2621 if (VA.isRegLoc()) {
2622 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2623 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2624 (ValVT == MVT::i64 && LocVT == MVT::f64))
2625 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2626 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2627 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2628 Arg, DAG.getConstant(0, MVT::i32));
2629 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2630 Arg, DAG.getConstant(1, MVT::i32));
2631 if (!Subtarget.isLittle())
2632 std::swap(Lo, Hi);
2633 unsigned LocRegLo = VA.getLocReg();
2634 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2635 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2636 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2637 continue;
2638 }
2639 }
2640 break;
2641 case CCValAssign::BCvt:
2642 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2643 break;
2644 case CCValAssign::SExtUpper:
2645 UseUpperBits = true;
2646 // Fallthrough
2647 case CCValAssign::SExt:
2648 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2649 break;
2650 case CCValAssign::ZExtUpper:
2651 UseUpperBits = true;
2652 // Fallthrough
2653 case CCValAssign::ZExt:
2654 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2655 break;
2656 case CCValAssign::AExtUpper:
2657 UseUpperBits = true;
2658 // Fallthrough
2659 case CCValAssign::AExt:
2660 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2661 break;
2662 }
2663
2664 if (UseUpperBits) {
2665 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2666 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2667 Arg = DAG.getNode(
2668 ISD::SHL, DL, VA.getLocVT(), Arg,
2669 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2670 }
2671
2672 // Arguments that can be passed on register must be kept at
2673 // RegsToPass vector
2674 if (VA.isRegLoc()) {
2675 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2676 continue;
2677 }
2678
2679 // Register can't get to this point...
2680 assert(VA.isMemLoc());
2681
2682 // emit ISD::STORE whichs stores the
2683 // parameter value to a stack Location
2684 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2685 Chain, Arg, DL, IsTailCall, DAG));
2686 }
2687
2688 // Transform all store nodes into one single node because all store
2689 // nodes are independent of each other.
2690 if (!MemOpChains.empty())
2691 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2692
2693 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2694 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2695 // node so that legalize doesn't hack it.
2696 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to
2697 // jalr $25
2698 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2699 SDValue CalleeLo;
2700 EVT Ty = Callee.getValueType();
2701
2702 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2703 if (IsPICCall) {
2704 const GlobalValue *Val = G->getGlobal();
2705 InternalLinkage = Val->hasInternalLinkage();
2706
2707 if (InternalLinkage)
2708 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
2709 else if (LargeGOT) {
2710 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2711 MipsII::MO_CALL_LO16, Chain,
2712 FuncInfo->callPtrInfo(Val));
2713 IsCallReloc = true;
2714 } else {
2715 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2716 FuncInfo->callPtrInfo(Val));
2717 IsCallReloc = true;
2718 }
2719 } else
2720 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2721 MipsII::MO_NO_FLAG);
2722 GlobalOrExternal = true;
2723 }
2724 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2725 const char *Sym = S->getSymbol();
2726
2727 if (!ABI.IsN64() && !IsPIC) // !N64 && static
2728 Callee =
2729 DAG.getTargetExternalSymbol(Sym, getPointerTy(), MipsII::MO_NO_FLAG);
2730 else if (LargeGOT) {
2731 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2732 MipsII::MO_CALL_LO16, Chain,
2733 FuncInfo->callPtrInfo(Sym));
2734 IsCallReloc = true;
2735 } else { // N64 || PIC
2736 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2737 FuncInfo->callPtrInfo(Sym));
2738 IsCallReloc = true;
2739 }
2740
2741 GlobalOrExternal = true;
2742 }
2743
2744 SmallVector<SDValue, 8> Ops(1, Chain);
2745 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2746
2747 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2748 IsCallReloc, CLI, Callee, Chain);
2749
2750 if (IsTailCall)
2751 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2752
2753 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2754 SDValue InFlag = Chain.getValue(1);
2755
2756 // Create the CALLSEQ_END node.
2757 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2758 DAG.getIntPtrConstant(0, true), InFlag, DL);
2759 InFlag = Chain.getValue(1);
2760
2761 // Handle result values, copying them out of physregs into vregs that we
2762 // return.
2763 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2764 InVals, CLI);
2765 }
2766
2767 /// LowerCallResult - Lower the result values of a call into the
2768 /// appropriate copies out of appropriate physical registers.
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,TargetLowering::CallLoweringInfo & CLI) const2769 SDValue MipsTargetLowering::LowerCallResult(
2770 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2771 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2772 SmallVectorImpl<SDValue> &InVals,
2773 TargetLowering::CallLoweringInfo &CLI) const {
2774 // Assign locations to each value returned by this call.
2775 SmallVector<CCValAssign, 16> RVLocs;
2776 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2777 *DAG.getContext());
2778 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2779
2780 // Copy all of the result registers out of their specified physreg.
2781 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2782 CCValAssign &VA = RVLocs[i];
2783 assert(VA.isRegLoc() && "Can only return in registers!");
2784
2785 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2786 RVLocs[i].getLocVT(), InFlag);
2787 Chain = Val.getValue(1);
2788 InFlag = Val.getValue(2);
2789
2790 if (VA.isUpperBitsInLoc()) {
2791 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2792 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2793 unsigned Shift =
2794 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2795 Val = DAG.getNode(
2796 Shift, DL, VA.getLocVT(), Val,
2797 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2798 }
2799
2800 switch (VA.getLocInfo()) {
2801 default:
2802 llvm_unreachable("Unknown loc info!");
2803 case CCValAssign::Full:
2804 break;
2805 case CCValAssign::BCvt:
2806 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2807 break;
2808 case CCValAssign::AExt:
2809 case CCValAssign::AExtUpper:
2810 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2811 break;
2812 case CCValAssign::ZExt:
2813 case CCValAssign::ZExtUpper:
2814 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2815 DAG.getValueType(VA.getValVT()));
2816 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2817 break;
2818 case CCValAssign::SExt:
2819 case CCValAssign::SExtUpper:
2820 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2821 DAG.getValueType(VA.getValVT()));
2822 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2823 break;
2824 }
2825
2826 InVals.push_back(Val);
2827 }
2828
2829 return Chain;
2830 }
2831
UnpackFromArgumentSlot(SDValue Val,const CCValAssign & VA,EVT ArgVT,SDLoc DL,SelectionDAG & DAG)2832 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
2833 EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
2834 MVT LocVT = VA.getLocVT();
2835 EVT ValVT = VA.getValVT();
2836
2837 // Shift into the upper bits if necessary.
2838 switch (VA.getLocInfo()) {
2839 default:
2840 break;
2841 case CCValAssign::AExtUpper:
2842 case CCValAssign::SExtUpper:
2843 case CCValAssign::ZExtUpper: {
2844 unsigned ValSizeInBits = ArgVT.getSizeInBits();
2845 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2846 unsigned Opcode =
2847 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2848 Val = DAG.getNode(
2849 Opcode, DL, VA.getLocVT(), Val,
2850 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
2851 break;
2852 }
2853 }
2854
2855 // If this is an value smaller than the argument slot size (32-bit for O32,
2856 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
2857 // size. Extract the value and insert any appropriate assertions regarding
2858 // sign/zero extension.
2859 switch (VA.getLocInfo()) {
2860 default:
2861 llvm_unreachable("Unknown loc info!");
2862 case CCValAssign::Full:
2863 break;
2864 case CCValAssign::AExtUpper:
2865 case CCValAssign::AExt:
2866 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2867 break;
2868 case CCValAssign::SExtUpper:
2869 case CCValAssign::SExt:
2870 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
2871 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2872 break;
2873 case CCValAssign::ZExtUpper:
2874 case CCValAssign::ZExt:
2875 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
2876 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2877 break;
2878 case CCValAssign::BCvt:
2879 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2880 break;
2881 }
2882
2883 return Val;
2884 }
2885
2886 //===----------------------------------------------------------------------===//
2887 // Formal Arguments Calling Convention Implementation
2888 //===----------------------------------------------------------------------===//
2889 /// LowerFormalArguments - transform physical registers into virtual registers
2890 /// and generate load operations for arguments places on the stack.
2891 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const2892 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2893 CallingConv::ID CallConv,
2894 bool IsVarArg,
2895 const SmallVectorImpl<ISD::InputArg> &Ins,
2896 SDLoc DL, SelectionDAG &DAG,
2897 SmallVectorImpl<SDValue> &InVals)
2898 const {
2899 MachineFunction &MF = DAG.getMachineFunction();
2900 MachineFrameInfo *MFI = MF.getFrameInfo();
2901 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2902
2903 MipsFI->setVarArgsFrameIndex(0);
2904
2905 // Used with vargs to acumulate store chains.
2906 std::vector<SDValue> OutChains;
2907
2908 // Assign locations to all of the incoming arguments.
2909 SmallVector<CCValAssign, 16> ArgLocs;
2910 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2911 *DAG.getContext());
2912 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2913 Function::const_arg_iterator FuncArg =
2914 DAG.getMachineFunction().getFunction()->arg_begin();
2915
2916 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
2917 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2918 CCInfo.getInRegsParamsCount() > 0);
2919
2920 unsigned CurArgIdx = 0;
2921 CCInfo.rewindByValRegsInfo();
2922
2923 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2924 CCValAssign &VA = ArgLocs[i];
2925 if (Ins[i].isOrigArg()) {
2926 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2927 CurArgIdx = Ins[i].getOrigArgIndex();
2928 }
2929 EVT ValVT = VA.getValVT();
2930 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2931 bool IsRegLoc = VA.isRegLoc();
2932
2933 if (Flags.isByVal()) {
2934 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
2935 unsigned FirstByValReg, LastByValReg;
2936 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2937 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2938
2939 assert(Flags.getByValSize() &&
2940 "ByVal args of size 0 should have been ignored by front-end.");
2941 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2942 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2943 FirstByValReg, LastByValReg, VA, CCInfo);
2944 CCInfo.nextInRegsParam();
2945 continue;
2946 }
2947
2948 // Arguments stored on registers
2949 if (IsRegLoc) {
2950 MVT RegVT = VA.getLocVT();
2951 unsigned ArgReg = VA.getLocReg();
2952 const TargetRegisterClass *RC = getRegClassFor(RegVT);
2953
2954 // Transform the arguments stored on
2955 // physical registers into virtual ones
2956 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2957 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2958
2959 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
2960
2961 // Handle floating point arguments passed in integer registers and
2962 // long double arguments passed in floating point registers.
2963 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2964 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2965 (RegVT == MVT::f64 && ValVT == MVT::i64))
2966 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2967 else if (ABI.IsO32() && RegVT == MVT::i32 &&
2968 ValVT == MVT::f64) {
2969 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2970 getNextIntArgReg(ArgReg), RC);
2971 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2972 if (!Subtarget.isLittle())
2973 std::swap(ArgValue, ArgValue2);
2974 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2975 ArgValue, ArgValue2);
2976 }
2977
2978 InVals.push_back(ArgValue);
2979 } else { // VA.isRegLoc()
2980 MVT LocVT = VA.getLocVT();
2981
2982 if (ABI.IsO32()) {
2983 // We ought to be able to use LocVT directly but O32 sets it to i32
2984 // when allocating floating point values to integer registers.
2985 // This shouldn't influence how we load the value into registers unless
2986 // we are targetting softfloat.
2987 if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat())
2988 LocVT = VA.getValVT();
2989 }
2990
2991 // sanity check
2992 assert(VA.isMemLoc());
2993
2994 // The stack pointer offset is relative to the caller stack frame.
2995 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
2996 VA.getLocMemOffset(), true);
2997
2998 // Create load nodes to retrieve arguments from the stack
2999 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3000 SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
3001 MachinePointerInfo::getFixedStack(FI),
3002 false, false, false, 0);
3003 OutChains.push_back(ArgValue.getValue(1));
3004
3005 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3006
3007 InVals.push_back(ArgValue);
3008 }
3009 }
3010
3011 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3012 // The mips ABIs for returning structs by value requires that we copy
3013 // the sret argument into $v0 for the return. Save the argument into
3014 // a virtual register so that we can access it from the return points.
3015 if (Ins[i].Flags.isSRet()) {
3016 unsigned Reg = MipsFI->getSRetReturnReg();
3017 if (!Reg) {
3018 Reg = MF.getRegInfo().createVirtualRegister(
3019 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3020 MipsFI->setSRetReturnReg(Reg);
3021 }
3022 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3023 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3024 break;
3025 }
3026 }
3027
3028 if (IsVarArg)
3029 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3030
3031 // All stores are grouped in one node to allow the matching between
3032 // the size of Ins and InVals. This only happens when on varg functions
3033 if (!OutChains.empty()) {
3034 OutChains.push_back(Chain);
3035 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3036 }
3037
3038 return Chain;
3039 }
3040
3041 //===----------------------------------------------------------------------===//
3042 // Return Value Calling Convention Implementation
3043 //===----------------------------------------------------------------------===//
3044
3045 bool
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const3046 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3047 MachineFunction &MF, bool IsVarArg,
3048 const SmallVectorImpl<ISD::OutputArg> &Outs,
3049 LLVMContext &Context) const {
3050 SmallVector<CCValAssign, 16> RVLocs;
3051 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3052 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3053 }
3054
3055 bool
shouldSignExtendTypeInLibCall(EVT Type,bool IsSigned) const3056 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3057 if (Subtarget.hasMips3() && Subtarget.abiUsesSoftFloat()) {
3058 if (Type == MVT::i32)
3059 return true;
3060 }
3061 return IsSigned;
3062 }
3063
3064 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const3065 MipsTargetLowering::LowerReturn(SDValue Chain,
3066 CallingConv::ID CallConv, bool IsVarArg,
3067 const SmallVectorImpl<ISD::OutputArg> &Outs,
3068 const SmallVectorImpl<SDValue> &OutVals,
3069 SDLoc DL, SelectionDAG &DAG) const {
3070 // CCValAssign - represent the assignment of
3071 // the return value to a location
3072 SmallVector<CCValAssign, 16> RVLocs;
3073 MachineFunction &MF = DAG.getMachineFunction();
3074
3075 // CCState - Info about the registers and stack slot.
3076 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3077
3078 // Analyze return values.
3079 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3080
3081 SDValue Flag;
3082 SmallVector<SDValue, 4> RetOps(1, Chain);
3083
3084 // Copy the result values into the output registers.
3085 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3086 SDValue Val = OutVals[i];
3087 CCValAssign &VA = RVLocs[i];
3088 assert(VA.isRegLoc() && "Can only return in registers!");
3089 bool UseUpperBits = false;
3090
3091 switch (VA.getLocInfo()) {
3092 default:
3093 llvm_unreachable("Unknown loc info!");
3094 case CCValAssign::Full:
3095 break;
3096 case CCValAssign::BCvt:
3097 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3098 break;
3099 case CCValAssign::AExtUpper:
3100 UseUpperBits = true;
3101 // Fallthrough
3102 case CCValAssign::AExt:
3103 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3104 break;
3105 case CCValAssign::ZExtUpper:
3106 UseUpperBits = true;
3107 // Fallthrough
3108 case CCValAssign::ZExt:
3109 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3110 break;
3111 case CCValAssign::SExtUpper:
3112 UseUpperBits = true;
3113 // Fallthrough
3114 case CCValAssign::SExt:
3115 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3116 break;
3117 }
3118
3119 if (UseUpperBits) {
3120 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3121 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3122 Val = DAG.getNode(
3123 ISD::SHL, DL, VA.getLocVT(), Val,
3124 DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
3125 }
3126
3127 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3128
3129 // Guarantee that all emitted copies are stuck together with flags.
3130 Flag = Chain.getValue(1);
3131 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3132 }
3133
3134 // The mips ABIs for returning structs by value requires that we copy
3135 // the sret argument into $v0 for the return. We saved the argument into
3136 // a virtual register in the entry block, so now we copy the value out
3137 // and into $v0.
3138 if (MF.getFunction()->hasStructRetAttr()) {
3139 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3140 unsigned Reg = MipsFI->getSRetReturnReg();
3141
3142 if (!Reg)
3143 llvm_unreachable("sret virtual register not created in the entry block");
3144 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
3145 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3146
3147 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3148 Flag = Chain.getValue(1);
3149 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
3150 }
3151
3152 RetOps[0] = Chain; // Update chain.
3153
3154 // Add the flag if we have it.
3155 if (Flag.getNode())
3156 RetOps.push_back(Flag);
3157
3158 // Return on Mips is always a "jr $ra"
3159 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3160 }
3161
3162 //===----------------------------------------------------------------------===//
3163 // Mips Inline Assembly Support
3164 //===----------------------------------------------------------------------===//
3165
3166 /// getConstraintType - Given a constraint letter, return the type of
3167 /// constraint it is for this target.
3168 MipsTargetLowering::ConstraintType MipsTargetLowering::
getConstraintType(const std::string & Constraint) const3169 getConstraintType(const std::string &Constraint) const
3170 {
3171 // Mips specific constraints
3172 // GCC config/mips/constraints.md
3173 //
3174 // 'd' : An address register. Equivalent to r
3175 // unless generating MIPS16 code.
3176 // 'y' : Equivalent to r; retained for
3177 // backwards compatibility.
3178 // 'c' : A register suitable for use in an indirect
3179 // jump. This will always be $25 for -mabicalls.
3180 // 'l' : The lo register. 1 word storage.
3181 // 'x' : The hilo register pair. Double word storage.
3182 if (Constraint.size() == 1) {
3183 switch (Constraint[0]) {
3184 default : break;
3185 case 'd':
3186 case 'y':
3187 case 'f':
3188 case 'c':
3189 case 'l':
3190 case 'x':
3191 return C_RegisterClass;
3192 case 'R':
3193 return C_Memory;
3194 }
3195 }
3196
3197 if (Constraint == "ZC")
3198 return C_Memory;
3199
3200 return TargetLowering::getConstraintType(Constraint);
3201 }
3202
3203 /// Examine constraint type and operand type and determine a weight value.
3204 /// This object must already have been set up with the operand type
3205 /// and the current alternative constraint selected.
3206 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3207 MipsTargetLowering::getSingleConstraintMatchWeight(
3208 AsmOperandInfo &info, const char *constraint) const {
3209 ConstraintWeight weight = CW_Invalid;
3210 Value *CallOperandVal = info.CallOperandVal;
3211 // If we don't have a value, we can't do a match,
3212 // but allow it at the lowest weight.
3213 if (!CallOperandVal)
3214 return CW_Default;
3215 Type *type = CallOperandVal->getType();
3216 // Look at the constraint type.
3217 switch (*constraint) {
3218 default:
3219 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3220 break;
3221 case 'd':
3222 case 'y':
3223 if (type->isIntegerTy())
3224 weight = CW_Register;
3225 break;
3226 case 'f': // FPU or MSA register
3227 if (Subtarget.hasMSA() && type->isVectorTy() &&
3228 cast<VectorType>(type)->getBitWidth() == 128)
3229 weight = CW_Register;
3230 else if (type->isFloatTy())
3231 weight = CW_Register;
3232 break;
3233 case 'c': // $25 for indirect jumps
3234 case 'l': // lo register
3235 case 'x': // hilo register pair
3236 if (type->isIntegerTy())
3237 weight = CW_SpecificReg;
3238 break;
3239 case 'I': // signed 16 bit immediate
3240 case 'J': // integer zero
3241 case 'K': // unsigned 16 bit immediate
3242 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3243 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3244 case 'O': // signed 15 bit immediate (+- 16383)
3245 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3246 if (isa<ConstantInt>(CallOperandVal))
3247 weight = CW_Constant;
3248 break;
3249 case 'R':
3250 weight = CW_Memory;
3251 break;
3252 }
3253 return weight;
3254 }
3255
3256 /// This is a helper function to parse a physical register string and split it
3257 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3258 /// that is returned indicates whether parsing was successful. The second flag
3259 /// is true if the numeric part exists.
3260 static std::pair<bool, bool>
parsePhysicalReg(StringRef C,std::string & Prefix,unsigned long long & Reg)3261 parsePhysicalReg(StringRef C, std::string &Prefix,
3262 unsigned long long &Reg) {
3263 if (C.front() != '{' || C.back() != '}')
3264 return std::make_pair(false, false);
3265
3266 // Search for the first numeric character.
3267 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3268 I = std::find_if(B, E, std::ptr_fun(isdigit));
3269
3270 Prefix.assign(B, I - B);
3271
3272 // The second flag is set to false if no numeric characters were found.
3273 if (I == E)
3274 return std::make_pair(true, false);
3275
3276 // Parse the numeric characters.
3277 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3278 true);
3279 }
3280
3281 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
parseRegForInlineAsmConstraint(StringRef C,MVT VT) const3282 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3283 const TargetRegisterInfo *TRI =
3284 Subtarget.getRegisterInfo();
3285 const TargetRegisterClass *RC;
3286 std::string Prefix;
3287 unsigned long long Reg;
3288
3289 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3290
3291 if (!R.first)
3292 return std::make_pair(0U, nullptr);
3293
3294 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3295 // No numeric characters follow "hi" or "lo".
3296 if (R.second)
3297 return std::make_pair(0U, nullptr);
3298
3299 RC = TRI->getRegClass(Prefix == "hi" ?
3300 Mips::HI32RegClassID : Mips::LO32RegClassID);
3301 return std::make_pair(*(RC->begin()), RC);
3302 } else if (Prefix.compare(0, 4, "$msa") == 0) {
3303 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3304
3305 // No numeric characters follow the name.
3306 if (R.second)
3307 return std::make_pair(0U, nullptr);
3308
3309 Reg = StringSwitch<unsigned long long>(Prefix)
3310 .Case("$msair", Mips::MSAIR)
3311 .Case("$msacsr", Mips::MSACSR)
3312 .Case("$msaaccess", Mips::MSAAccess)
3313 .Case("$msasave", Mips::MSASave)
3314 .Case("$msamodify", Mips::MSAModify)
3315 .Case("$msarequest", Mips::MSARequest)
3316 .Case("$msamap", Mips::MSAMap)
3317 .Case("$msaunmap", Mips::MSAUnmap)
3318 .Default(0);
3319
3320 if (!Reg)
3321 return std::make_pair(0U, nullptr);
3322
3323 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3324 return std::make_pair(Reg, RC);
3325 }
3326
3327 if (!R.second)
3328 return std::make_pair(0U, nullptr);
3329
3330 if (Prefix == "$f") { // Parse $f0-$f31.
3331 // If the size of FP registers is 64-bit or Reg is an even number, select
3332 // the 64-bit register class. Otherwise, select the 32-bit register class.
3333 if (VT == MVT::Other)
3334 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3335
3336 RC = getRegClassFor(VT);
3337
3338 if (RC == &Mips::AFGR64RegClass) {
3339 assert(Reg % 2 == 0);
3340 Reg >>= 1;
3341 }
3342 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3343 RC = TRI->getRegClass(Mips::FCCRegClassID);
3344 else if (Prefix == "$w") { // Parse $w0-$w31.
3345 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3346 } else { // Parse $0-$31.
3347 assert(Prefix == "$");
3348 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3349 }
3350
3351 assert(Reg < RC->getNumRegs());
3352 return std::make_pair(*(RC->begin() + Reg), RC);
3353 }
3354
3355 /// Given a register class constraint, like 'r', if this corresponds directly
3356 /// to an LLVM register class, return a register of 0 and the register class
3357 /// pointer.
3358 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,const std::string & Constraint,MVT VT) const3359 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3360 const std::string &Constraint,
3361 MVT VT) const {
3362 if (Constraint.size() == 1) {
3363 switch (Constraint[0]) {
3364 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3365 case 'y': // Same as 'r'. Exists for compatibility.
3366 case 'r':
3367 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3368 if (Subtarget.inMips16Mode())
3369 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3370 return std::make_pair(0U, &Mips::GPR32RegClass);
3371 }
3372 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3373 return std::make_pair(0U, &Mips::GPR32RegClass);
3374 if (VT == MVT::i64 && Subtarget.isGP64bit())
3375 return std::make_pair(0U, &Mips::GPR64RegClass);
3376 // This will generate an error message
3377 return std::make_pair(0U, nullptr);
3378 case 'f': // FPU or MSA register
3379 if (VT == MVT::v16i8)
3380 return std::make_pair(0U, &Mips::MSA128BRegClass);
3381 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3382 return std::make_pair(0U, &Mips::MSA128HRegClass);
3383 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3384 return std::make_pair(0U, &Mips::MSA128WRegClass);
3385 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3386 return std::make_pair(0U, &Mips::MSA128DRegClass);
3387 else if (VT == MVT::f32)
3388 return std::make_pair(0U, &Mips::FGR32RegClass);
3389 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3390 if (Subtarget.isFP64bit())
3391 return std::make_pair(0U, &Mips::FGR64RegClass);
3392 return std::make_pair(0U, &Mips::AFGR64RegClass);
3393 }
3394 break;
3395 case 'c': // register suitable for indirect jump
3396 if (VT == MVT::i32)
3397 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3398 assert(VT == MVT::i64 && "Unexpected type.");
3399 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3400 case 'l': // register suitable for indirect jump
3401 if (VT == MVT::i32)
3402 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3403 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3404 case 'x': // register suitable for indirect jump
3405 // Fixme: Not triggering the use of both hi and low
3406 // This will generate an error message
3407 return std::make_pair(0U, nullptr);
3408 }
3409 }
3410
3411 std::pair<unsigned, const TargetRegisterClass *> R;
3412 R = parseRegForInlineAsmConstraint(Constraint, VT);
3413
3414 if (R.second)
3415 return R;
3416
3417 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3418 }
3419
3420 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3421 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3422 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3423 std::string &Constraint,
3424 std::vector<SDValue>&Ops,
3425 SelectionDAG &DAG) const {
3426 SDValue Result;
3427
3428 // Only support length 1 constraints for now.
3429 if (Constraint.length() > 1) return;
3430
3431 char ConstraintLetter = Constraint[0];
3432 switch (ConstraintLetter) {
3433 default: break; // This will fall through to the generic implementation
3434 case 'I': // Signed 16 bit constant
3435 // If this fails, the parent routine will give an error
3436 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3437 EVT Type = Op.getValueType();
3438 int64_t Val = C->getSExtValue();
3439 if (isInt<16>(Val)) {
3440 Result = DAG.getTargetConstant(Val, Type);
3441 break;
3442 }
3443 }
3444 return;
3445 case 'J': // integer zero
3446 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3447 EVT Type = Op.getValueType();
3448 int64_t Val = C->getZExtValue();
3449 if (Val == 0) {
3450 Result = DAG.getTargetConstant(0, Type);
3451 break;
3452 }
3453 }
3454 return;
3455 case 'K': // unsigned 16 bit immediate
3456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3457 EVT Type = Op.getValueType();
3458 uint64_t Val = (uint64_t)C->getZExtValue();
3459 if (isUInt<16>(Val)) {
3460 Result = DAG.getTargetConstant(Val, Type);
3461 break;
3462 }
3463 }
3464 return;
3465 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3467 EVT Type = Op.getValueType();
3468 int64_t Val = C->getSExtValue();
3469 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3470 Result = DAG.getTargetConstant(Val, Type);
3471 break;
3472 }
3473 }
3474 return;
3475 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3477 EVT Type = Op.getValueType();
3478 int64_t Val = C->getSExtValue();
3479 if ((Val >= -65535) && (Val <= -1)) {
3480 Result = DAG.getTargetConstant(Val, Type);
3481 break;
3482 }
3483 }
3484 return;
3485 case 'O': // signed 15 bit immediate
3486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3487 EVT Type = Op.getValueType();
3488 int64_t Val = C->getSExtValue();
3489 if ((isInt<15>(Val))) {
3490 Result = DAG.getTargetConstant(Val, Type);
3491 break;
3492 }
3493 }
3494 return;
3495 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3497 EVT Type = Op.getValueType();
3498 int64_t Val = C->getSExtValue();
3499 if ((Val <= 65535) && (Val >= 1)) {
3500 Result = DAG.getTargetConstant(Val, Type);
3501 break;
3502 }
3503 }
3504 return;
3505 }
3506
3507 if (Result.getNode()) {
3508 Ops.push_back(Result);
3509 return;
3510 }
3511
3512 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3513 }
3514
isLegalAddressingMode(const AddrMode & AM,Type * Ty) const3515 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3516 Type *Ty) const {
3517 // No global is ever allowed as a base.
3518 if (AM.BaseGV)
3519 return false;
3520
3521 switch (AM.Scale) {
3522 case 0: // "r+i" or just "i", depending on HasBaseReg.
3523 break;
3524 case 1:
3525 if (!AM.HasBaseReg) // allow "r+i".
3526 break;
3527 return false; // disallow "r+r" or "r+r+i".
3528 default:
3529 return false;
3530 }
3531
3532 return true;
3533 }
3534
3535 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3536 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3537 // The Mips target isn't yet aware of offsets.
3538 return false;
3539 }
3540
getOptimalMemOpType(uint64_t Size,unsigned DstAlign,unsigned SrcAlign,bool IsMemset,bool ZeroMemset,bool MemcpyStrSrc,MachineFunction & MF) const3541 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3542 unsigned SrcAlign,
3543 bool IsMemset, bool ZeroMemset,
3544 bool MemcpyStrSrc,
3545 MachineFunction &MF) const {
3546 if (Subtarget.hasMips64())
3547 return MVT::i64;
3548
3549 return MVT::i32;
3550 }
3551
isFPImmLegal(const APFloat & Imm,EVT VT) const3552 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3553 if (VT != MVT::f32 && VT != MVT::f64)
3554 return false;
3555 if (Imm.isNegZero())
3556 return false;
3557 return Imm.isZero();
3558 }
3559
getJumpTableEncoding() const3560 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3561 if (ABI.IsN64())
3562 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3563
3564 return TargetLowering::getJumpTableEncoding();
3565 }
3566
copyByValRegs(SDValue Chain,SDLoc DL,std::vector<SDValue> & OutChains,SelectionDAG & DAG,const ISD::ArgFlagsTy & Flags,SmallVectorImpl<SDValue> & InVals,const Argument * FuncArg,unsigned FirstReg,unsigned LastReg,const CCValAssign & VA,MipsCCState & State) const3567 void MipsTargetLowering::copyByValRegs(
3568 SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3569 const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
3570 const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
3571 const CCValAssign &VA, MipsCCState &State) const {
3572 MachineFunction &MF = DAG.getMachineFunction();
3573 MachineFrameInfo *MFI = MF.getFrameInfo();
3574 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3575 unsigned NumRegs = LastReg - FirstReg;
3576 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3577 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3578 int FrameObjOffset;
3579 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3580
3581 if (RegAreaSize)
3582 FrameObjOffset =
3583 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3584 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3585 else
3586 FrameObjOffset = VA.getLocMemOffset();
3587
3588 // Create frame object.
3589 EVT PtrTy = getPointerTy();
3590 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3591 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3592 InVals.push_back(FIN);
3593
3594 if (!NumRegs)
3595 return;
3596
3597 // Copy arg registers.
3598 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3599 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3600
3601 for (unsigned I = 0; I < NumRegs; ++I) {
3602 unsigned ArgReg = ByValArgRegs[FirstReg + I];
3603 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3604 unsigned Offset = I * GPRSizeInBytes;
3605 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3606 DAG.getConstant(Offset, PtrTy));
3607 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3608 StorePtr, MachinePointerInfo(FuncArg, Offset),
3609 false, false, 0);
3610 OutChains.push_back(Store);
3611 }
3612 }
3613
3614 // Copy byVal arg to registers and stack.
passByValArg(SDValue Chain,SDLoc DL,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,SmallVectorImpl<SDValue> & MemOpChains,SDValue StackPtr,MachineFrameInfo * MFI,SelectionDAG & DAG,SDValue Arg,unsigned FirstReg,unsigned LastReg,const ISD::ArgFlagsTy & Flags,bool isLittle,const CCValAssign & VA) const3615 void MipsTargetLowering::passByValArg(
3616 SDValue Chain, SDLoc DL,
3617 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3618 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3619 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3620 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3621 const CCValAssign &VA) const {
3622 unsigned ByValSizeInBytes = Flags.getByValSize();
3623 unsigned OffsetInBytes = 0; // From beginning of struct
3624 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3625 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3626 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3627 unsigned NumRegs = LastReg - FirstReg;
3628
3629 if (NumRegs) {
3630 const ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
3631 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3632 unsigned I = 0;
3633
3634 // Copy words to registers.
3635 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3636 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3637 DAG.getConstant(OffsetInBytes, PtrTy));
3638 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3639 MachinePointerInfo(), false, false, false,
3640 Alignment);
3641 MemOpChains.push_back(LoadVal.getValue(1));
3642 unsigned ArgReg = ArgRegs[FirstReg + I];
3643 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3644 }
3645
3646 // Return if the struct has been fully copied.
3647 if (ByValSizeInBytes == OffsetInBytes)
3648 return;
3649
3650 // Copy the remainder of the byval argument with sub-word loads and shifts.
3651 if (LeftoverBytes) {
3652 SDValue Val;
3653
3654 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3655 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3656 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3657
3658 if (RemainingSizeInBytes < LoadSizeInBytes)
3659 continue;
3660
3661 // Load subword.
3662 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3663 DAG.getConstant(OffsetInBytes, PtrTy));
3664 SDValue LoadVal = DAG.getExtLoad(
3665 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3666 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3667 Alignment);
3668 MemOpChains.push_back(LoadVal.getValue(1));
3669
3670 // Shift the loaded value.
3671 unsigned Shamt;
3672
3673 if (isLittle)
3674 Shamt = TotalBytesLoaded * 8;
3675 else
3676 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3677
3678 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3679 DAG.getConstant(Shamt, MVT::i32));
3680
3681 if (Val.getNode())
3682 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3683 else
3684 Val = Shift;
3685
3686 OffsetInBytes += LoadSizeInBytes;
3687 TotalBytesLoaded += LoadSizeInBytes;
3688 Alignment = std::min(Alignment, LoadSizeInBytes);
3689 }
3690
3691 unsigned ArgReg = ArgRegs[FirstReg + I];
3692 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3693 return;
3694 }
3695 }
3696
3697 // Copy remainder of byval arg to it with memcpy.
3698 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3699 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3700 DAG.getConstant(OffsetInBytes, PtrTy));
3701 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3702 DAG.getIntPtrConstant(VA.getLocMemOffset()));
3703 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
3704 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3705 /*isTailCall=*/false,
3706 MachinePointerInfo(), MachinePointerInfo());
3707 MemOpChains.push_back(Chain);
3708 }
3709
writeVarArgRegs(std::vector<SDValue> & OutChains,SDValue Chain,SDLoc DL,SelectionDAG & DAG,CCState & State) const3710 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3711 SDValue Chain, SDLoc DL,
3712 SelectionDAG &DAG,
3713 CCState &State) const {
3714 const ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
3715 unsigned Idx = State.getFirstUnallocated(ArgRegs);
3716 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3717 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3718 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3719 MachineFunction &MF = DAG.getMachineFunction();
3720 MachineFrameInfo *MFI = MF.getFrameInfo();
3721 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3722
3723 // Offset of the first variable argument from stack pointer.
3724 int VaArgOffset;
3725
3726 if (ArgRegs.size() == Idx)
3727 VaArgOffset =
3728 RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
3729 else {
3730 VaArgOffset =
3731 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3732 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3733 }
3734
3735 // Record the frame index of the first variable argument
3736 // which is a value necessary to VASTART.
3737 int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3738 MipsFI->setVarArgsFrameIndex(FI);
3739
3740 // Copy the integer registers that have not been used for argument passing
3741 // to the argument register save area. For O32, the save area is allocated
3742 // in the caller's stack frame, while for N32/64, it is allocated in the
3743 // callee's stack frame.
3744 for (unsigned I = Idx; I < ArgRegs.size();
3745 ++I, VaArgOffset += RegSizeInBytes) {
3746 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3747 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3748 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3749 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3750 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3751 MachinePointerInfo(), false, false, 0);
3752 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3753 (Value *)nullptr);
3754 OutChains.push_back(Store);
3755 }
3756 }
3757
HandleByVal(CCState * State,unsigned & Size,unsigned Align) const3758 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3759 unsigned Align) const {
3760 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3761
3762 assert(Size && "Byval argument's size shouldn't be 0.");
3763
3764 Align = std::min(Align, TFL->getStackAlignment());
3765
3766 unsigned FirstReg = 0;
3767 unsigned NumRegs = 0;
3768
3769 if (State->getCallingConv() != CallingConv::Fast) {
3770 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3771 const ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
3772 // FIXME: The O32 case actually describes no shadow registers.
3773 const MCPhysReg *ShadowRegs =
3774 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
3775
3776 // We used to check the size as well but we can't do that anymore since
3777 // CCState::HandleByVal() rounds up the size after calling this function.
3778 assert(!(Align % RegSizeInBytes) &&
3779 "Byval argument's alignment should be a multiple of"
3780 "RegSizeInBytes.");
3781
3782 FirstReg = State->getFirstUnallocated(IntArgRegs);
3783
3784 // If Align > RegSizeInBytes, the first arg register must be even.
3785 // FIXME: This condition happens to do the right thing but it's not the
3786 // right way to test it. We want to check that the stack frame offset
3787 // of the register is aligned.
3788 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3789 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3790 ++FirstReg;
3791 }
3792
3793 // Mark the registers allocated.
3794 Size = RoundUpToAlignment(Size, RegSizeInBytes);
3795 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3796 Size -= RegSizeInBytes, ++I, ++NumRegs)
3797 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3798 }
3799
3800 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3801 }
3802
3803 MachineBasicBlock *
emitPseudoSELECT(MachineInstr * MI,MachineBasicBlock * BB,bool isFPCmp,unsigned Opc) const3804 MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB,
3805 bool isFPCmp, unsigned Opc) const {
3806 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
3807 "Subtarget already supports SELECT nodes with the use of"
3808 "conditional-move instructions.");
3809
3810 const TargetInstrInfo *TII =
3811 Subtarget.getInstrInfo();
3812 DebugLoc DL = MI->getDebugLoc();
3813
3814 // To "insert" a SELECT instruction, we actually have to insert the
3815 // diamond control-flow pattern. The incoming instruction knows the
3816 // destination vreg to set, the condition code register to branch on, the
3817 // true/false values to select between, and a branch opcode to use.
3818 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3819 MachineFunction::iterator It = BB;
3820 ++It;
3821
3822 // thisMBB:
3823 // ...
3824 // TrueVal = ...
3825 // setcc r1, r2, r3
3826 // bNE r1, r0, copy1MBB
3827 // fallthrough --> copy0MBB
3828 MachineBasicBlock *thisMBB = BB;
3829 MachineFunction *F = BB->getParent();
3830 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3831 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3832 F->insert(It, copy0MBB);
3833 F->insert(It, sinkMBB);
3834
3835 // Transfer the remainder of BB and its successor edges to sinkMBB.
3836 sinkMBB->splice(sinkMBB->begin(), BB,
3837 std::next(MachineBasicBlock::iterator(MI)), BB->end());
3838 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3839
3840 // Next, add the true and fallthrough blocks as its successors.
3841 BB->addSuccessor(copy0MBB);
3842 BB->addSuccessor(sinkMBB);
3843
3844 if (isFPCmp) {
3845 // bc1[tf] cc, sinkMBB
3846 BuildMI(BB, DL, TII->get(Opc))
3847 .addReg(MI->getOperand(1).getReg())
3848 .addMBB(sinkMBB);
3849 } else {
3850 // bne rs, $0, sinkMBB
3851 BuildMI(BB, DL, TII->get(Opc))
3852 .addReg(MI->getOperand(1).getReg())
3853 .addReg(Mips::ZERO)
3854 .addMBB(sinkMBB);
3855 }
3856
3857 // copy0MBB:
3858 // %FalseValue = ...
3859 // # fallthrough to sinkMBB
3860 BB = copy0MBB;
3861
3862 // Update machine-CFG edges
3863 BB->addSuccessor(sinkMBB);
3864
3865 // sinkMBB:
3866 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
3867 // ...
3868 BB = sinkMBB;
3869
3870 BuildMI(*BB, BB->begin(), DL,
3871 TII->get(Mips::PHI), MI->getOperand(0).getReg())
3872 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
3873 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
3874
3875 MI->eraseFromParent(); // The pseudo instruction is gone now.
3876
3877 return BB;
3878 }
3879
3880 // FIXME? Maybe this could be a TableGen attribute on some registers and
3881 // this table could be generated automatically from RegInfo.
getRegisterByName(const char * RegName,EVT VT) const3882 unsigned MipsTargetLowering::getRegisterByName(const char* RegName,
3883 EVT VT) const {
3884 // Named registers is expected to be fairly rare. For now, just support $28
3885 // since the linux kernel uses it.
3886 if (Subtarget.isGP64bit()) {
3887 unsigned Reg = StringSwitch<unsigned>(RegName)
3888 .Case("$28", Mips::GP_64)
3889 .Default(0);
3890 if (Reg)
3891 return Reg;
3892 } else {
3893 unsigned Reg = StringSwitch<unsigned>(RegName)
3894 .Case("$28", Mips::GP)
3895 .Default(0);
3896 if (Reg)
3897 return Reg;
3898 }
3899 report_fatal_error("Invalid register name global variable");
3900 }
3901