Home
last modified time | relevance | path

Searched refs:CondCode (Results 1 – 25 of 74) sorted by relevance

123

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h779 enum CondCode { enum
812 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
818 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
825 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
833 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
839 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
843 CondCode getSetCCSwappedOperands(CondCode Operation);
849 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
855 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
DAnalysis.h84 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
88 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
93 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
/external/llvm/lib/Target/AArch64/
DAArch64ConditionOptimizer.cpp93 typedef std::tuple<int, int, AArch64CC::CondCode> CmpInfo;
99 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
101 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
204 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) { in getAdjustedCmp()
218 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { in adjustCmp()
249 AArch64CC::CondCode Cmp; in modifyCmp()
280 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
284 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
294 AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm) in adjustTo()
347 AArch64CC::CondCode HeadCmp; in runOnMachineFunction()
[all …]
DAArch64ConditionalCompares.cpp165 AArch64CC::CondCode HeadCmpBBCC;
171 AArch64CC::CondCode CmpBBTailCC;
272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
276 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
DAArch64ISelLowering.cpp929 unsigned CondCode = MI->getOperand(3).getImm(); in EmitF128CSEL() local
942 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); in EmitF128CSEL()
994 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { in changeIntCCToAArch64CC()
1022 static void changeFPCCToAArch64CC(ISD::CondCode CC, in changeFPCCToAArch64CC()
1023 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC() argument
1024 AArch64CC::CondCode &CondCode2) { in changeFPCCToAArch64CC()
1031 CondCode = AArch64CC::EQ; in changeFPCCToAArch64CC()
1035 CondCode = AArch64CC::GT; in changeFPCCToAArch64CC()
1039 CondCode = AArch64CC::GE; in changeFPCCToAArch64CC()
1042 CondCode = AArch64CC::MI; in changeFPCCToAArch64CC()
[all …]
DAArch64BranchRelaxation.cpp347 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm(); in invertBccCondition()
DAArch64InstrInfo.cpp189 AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in ReverseBranchCondition()
420 AArch64CC::CondCode CC; in insertSelect()
425 CC = AArch64CC::CondCode(Cond[0].getImm()); in insertSelect()
928 AArch64CC::CondCode CC; in optimizeCompareInstr()
933 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm(); in optimizeCompareInstr()
945 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
2943 AArch64CC::CondCode CC = in optimizeCondBranch()
2944 (AArch64CC::CondCode)DefMI->getOperand(3).getImm(); in optimizeCondBranch()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp38 enum CondCode { enum
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
243 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in AnalyzeBranch()
297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
420 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h32 enum CondCode { enum
63 unsigned GetCondBranchFromCond(CondCode CC);
67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
75 CondCode getCondFromCMovOpc(unsigned Opc);
79 CondCode GetOppositeBranchCondition(CondCode CC);
/external/mesa3d/src/gallium/drivers/nv50/codegen/
Dnv50_ir_inlines.h26 static inline CondCode reverseCondCode(CondCode cc) in reverseCondCode()
30 return static_cast<CondCode>(ccRev[cc & 7] | (cc & ~7)); in reverseCondCode()
33 static inline CondCode inverseCondCode(CondCode cc) in inverseCondCode()
35 return static_cast<CondCode>(cc ^ 7); in inverseCondCode()
Dnv50_ir.h168 enum CondCode enum
587 bool compare(CondCode cc, float fval) const;
629 bool setPredicate(CondCode ccode, Value *);
679 CondCode cc;
826 void setCondition(CondCode cond) { setCond = cond; } in setCondition()
827 CondCode getCondition() const { return setCond; } in getCondition()
830 CondCode setCond;
Dnv50_ir_build_util.h73 CmpInstruction *mkCmp(operation, CondCode, DataType,
80 FlowInstruction *mkFlow(operation, void *target, CondCode, Value *pred);
Dnv50_ir_build_util.cpp223 BuildUtil::mkCmp(operation op, CondCode cc, DataType ty, Value *dst, in mkCmp()
307 BuildUtil::mkFlow(operation op, void *targ, CondCode cc, Value *pred) in mkFlow()
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.h33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
DMipsInstPrinter.cpp37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
261 O << MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td537 class CondCode; // ISD::CondCode enums
538 def SETOEQ : CondCode; def SETOGT : CondCode;
539 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
540 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
541 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
542 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
544 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
545 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
DTargetLowering.h657 getCondCodeAction(ISD::CondCode CC, MVT VT) const { in getCondCodeAction()
670 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { in isCondCodeLegal()
1337 void setCondCodeAction(ISD::CondCode CC, MVT VT, in setCondCodeAction()
1662 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { in setCmpLibcallCC()
1668 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { in getCmpLibcallCC()
1886 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2031 ISD::CondCode &CCCode, SDLoc DL) const;
2144 ISD::CondCode Cond, bool foldBooleans,
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h192 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
213 inline static const char *getCondCodeName(CondCode Code) { in getCondCodeName()
235 inline static CondCode getInvertedCondCode(CondCode Code) { in getInvertedCondCode()
238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); in getInvertedCondCode()
245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { in getNZCVToSatisfyCondCode()
/external/llvm/lib/CodeGen/
DAnalysis.cpp161 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
183 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
198 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp259 const ISD::CondCode Cond; in ARMTargetLowering()
1217 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { in IntCCToARMCC()
1234 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC() argument
1240 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
1242 case ISD::SETOGT: CondCode = ARMCC::GT; break; in FPCCToARMCC()
1244 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
1245 case ISD::SETOLT: CondCode = ARMCC::MI; break; in FPCCToARMCC()
1246 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
1247 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; in FPCCToARMCC()
1248 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
[all …]
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp58 AArch64CC::CondCode parseCondCodeString(StringRef Cond);
198 AArch64CC::CondCode Code;
246 struct CondCodeOp CondCode; member
277 CondCode = o.CondCode; in AArch64Operand()
339 AArch64CC::CondCode getCondCode() const { in getCondCode()
341 return CondCode.Code; in getCondCode()
1595 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateCondCode()
1597 Op->CondCode.Code = Code; in CreateCondCode()
2206 AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) { in parseCondCodeString()
2207 AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower()) in parseCondCodeString()
[all …]
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp465 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { in NegateCC()
481 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
498 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.h176 unsigned CondCode = 0) const;
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1051 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); in printCondCode()
1058 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); in printInverseCondCode()
/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp1148 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1149 ISD::CondCode InverseCC = in LowerSELECT_CC()
1156 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC); in LowerSELECT_CC()
1183 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1185 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
1191 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger()); in LowerSELECT_CC()
1203 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1972 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in PerformDAGCombine()
1984 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get(); in PerformDAGCombine()

123