| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.h | 48 DAGCombinerInfo &DCI) const;
51 DAGCombinerInfo &DCI) const;
52 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
53 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
54 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
56 SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
57 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
97 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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| D | SIISelLowering.cpp | 1247 DAGCombinerInfo &DCI) const { in performUCharToFloatCombine()
1253 SelectionDAG &DAG = DCI.DAG; in performUCharToFloatCombine()
1263 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
1266 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
1275 if (!DCI.isBeforeLegalize() || in performUCharToFloatCombine()
1281 assert(DCI.isBeforeLegalize() && "Unexpected legal type"); in performUCharToFloatCombine()
1334 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
1394 DAGCombinerInfo &DCI) const { in performSHLPtrCombine()
1415 SelectionDAG &DAG = DCI.DAG; in performSHLPtrCombine()
1426 DAGCombinerInfo &DCI) const { in performAndCombine()
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| D | AMDGPUISelLowering.h | 67 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
148 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
162 DAGCombinerInfo &DCI) const;
175 DAGCombinerInfo &DCI,
179 DAGCombinerInfo &DCI,
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| D | AMDGPUISelLowering.cpp | 1075 DAGCombinerInfo &DCI) const { in CombineFMinMaxLegacy()
1082 SelectionDAG &DAG = DCI.DAG; in CombineFMinMaxLegacy()
1112 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && in CombineFMinMaxLegacy()
1113 !DCI.isCalledByLegalizer()) in CombineFMinMaxLegacy()
1133 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && in CombineFMinMaxLegacy()
1134 !DCI.isCalledByLegalizer()) in CombineFMinMaxLegacy()
2294 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) { in simplifyI24() argument
2296 SelectionDAG &DAG = DCI.DAG; in simplifyI24()
2304 DCI.CommitTargetLoweringOpt(TLO); in simplifyI24()
2333 DAGCombinerInfo &DCI) const { in performStoreCombine()
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| D | R600ISelLowering.h | 30 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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| D | R600ISelLowering.cpp | 1127 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr); in LowerSELECT_CC() local
1128 SDValue MinMax = CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI); in LowerSELECT_CC()
1836 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
1837 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
1840 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
1955 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
1987 if (DCI.isBeforeLegalizeOps() || in PerformDAGCombine()
2052 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 462 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
463 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
465 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
823 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
824 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
825 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
827 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
830 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
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| D | PPCISelLowering.cpp | 8852 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
8870 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand); in getRsqrtEstimate()
8876 DAGCombinerInfo &DCI, in getRecipEstimate() argument
8892 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand); in getRecipEstimate()
9126 DAGCombinerInfo &DCI) const { in DAGCombineTruncBoolExt()
9127 SelectionDAG &DAG = DCI.DAG; in DAGCombineTruncBoolExt()
9404 DAGCombinerInfo &DCI) const { in DAGCombineExtBoolTrunc()
9405 SelectionDAG &DAG = DCI.DAG; in DAGCombineExtBoolTrunc()
9682 DAGCombinerInfo &DCI) const { in combineFPToIntToFP()
9690 SelectionDAG &DAG = DCI.DAG; in combineFPToIntToFP()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1218 DAGCombinerInfo &DCI, SDLoc dl) const { in SimplifySetCC() argument
1219 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC()
1239 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1298 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
1352 if (DCI.isBeforeLegalize() && in SimplifySetCC()
1445 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1481 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
1482 DCI.AddToWorklist(ZextOp.getNode()); in SimplifySetCC()
1502 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1592 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7710 TargetLowering::DAGCombinerInfo &DCI, in combineSelectAndUse() argument
7712 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse()
7736 TargetLowering::DAGCombinerInfo &DCI) { in combineSelectAndUseCommutative() argument
7740 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes); in combineSelectAndUseCommutative()
7745 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes); in combineSelectAndUseCommutative()
7755 TargetLowering::DAGCombinerInfo &DCI, in AddCombineToVPADDL() argument
7760 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineToVPADDL()
7814 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADDL()
7851 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64bitMLAL() argument
7857 if (DCI.isBeforeLegalize()) return SDValue(); in AddCombineTo64bitMLAL()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 6914 TargetLowering::DAGCombinerInfo &DCI, in performXorCombine() argument
6916 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
6965 TargetLowering::DAGCombinerInfo &DCI, in performMulCombine() argument
6967 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
7134 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToEXTR() argument
7135 SelectionDAG &DAG = DCI.DAG; in tryCombineToEXTR()
7174 TargetLowering::DAGCombinerInfo &DCI) { in tryCombineToBSL() argument
7176 SelectionDAG &DAG = DCI.DAG; in tryCombineToBSL()
7220 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
7225 SelectionDAG &DAG = DCI.DAG; in performORCombine()
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| D | AArch64ISelLowering.h | 256 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIISelLowering.h | 53 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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| D | SIISelLowering.cpp | 393 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
394 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
430 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL); in PerformDAGCombine()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 529 TargetLowering::DAGCombinerInfo &DCI, in performADDECombine() argument
531 if (DCI.isBeforeLegalize()) in performADDECombine()
549 TargetLowering::DAGCombinerInfo &DCI, in performANDCombine() argument
664 TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
784 TargetLowering::DAGCombinerInfo &DCI, in performSUBECombine() argument
786 if (DCI.isBeforeLegalize()) in performSUBECombine()
835 const TargetLowering::DAGCombinerInfo &DCI, in performMULCombine() argument
872 TargetLowering::DAGCombinerInfo &DCI, in performSHLCombine() argument
895 TargetLowering::DAGCombinerInfo &DCI, in performSRACombine() argument
941 TargetLowering::DAGCombinerInfo &DCI, in performSRLCombine() argument
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| D | MipsSEISelLowering.h | 40 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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| D | MipsISelLowering.cpp | 452 TargetLowering::DAGCombinerInfo &DCI, in performDivRemCombine() argument
454 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
562 TargetLowering::DAGCombinerInfo &DCI, in performSELECTCombine() argument
564 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
641 TargetLowering::DAGCombinerInfo &DCI, in performCMovFPCombine() argument
643 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
668 TargetLowering::DAGCombinerInfo &DCI, in performANDCombine() argument
673 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
708 TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
714 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 3828 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombineWithOperands() argument
3831 SelectionDAG &DAG = DCI.DAG; in PerformADDCombineWithOperands()
3934 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombine() argument
3941 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, in PerformADDCombine()
3947 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel); in PerformADDCombine()
3951 TargetLowering::DAGCombinerInfo &DCI) { in PerformANDCombine() argument
4013 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), in PerformANDCombine()
4019 DCI.CombineTo(N, Val, AddTo); in PerformANDCombine()
4108 TargetLowering::DAGCombinerInfo &DCI) { in TryMULWIDECombine() argument
4136 RHS = DCI.DAG.getConstant(MulVal, MulType); in TryMULWIDECombine()
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| D | NVPTXISelLowering.h | 544 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 12769 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
12792 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op); in getRsqrtEstimate()
12800 DAGCombinerInfo &DCI, in getRecipEstimate() argument
12821 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op); in getRecipEstimate()
19444 TargetLowering::DAGCombinerInfo &DCI, in PerformShuffleCombine256() argument
19513 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
19524 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
19531 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
19548 TargetLowering::DAGCombinerInfo &DCI, in combineX86ShuffleChain() argument
19564 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input), in combineX86ShuffleChain()
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| D | X86ISelLowering.h | 630 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
1068 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1073 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1615 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
1616 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
1631 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1632 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1637 DCI.CommitTargetLoweringOpt(TLO); in PerformDAGCombine()
1648 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1649 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1654 DCI.CommitTargetLoweringOpt(TLO); in PerformDAGCombine()
1812 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
1826 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); in PerformDAGCombine()
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| D | XCoreISelLowering.h | 190 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 2145 DAGCombinerInfo &DCI, SDLoc dl) const;
2165 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2701 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
2716 DAGCombinerInfo &DCI, in getRecipEstimate() argument
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 290 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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