Searched refs:DestRC (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
40 if (DestRC != SrcRC) in copyPhysReg()
43 if (DestRC == &NVPTX::Int32RegsRegClass) in copyPhysReg()
46 else if (DestRC == &NVPTX::Int1RegsRegClass) in copyPhysReg()
49 else if (DestRC == &NVPTX::Float32RegsRegClass) in copyPhysReg()
52 else if (DestRC == &NVPTX::Int16RegsRegClass) in copyPhysReg()
55 else if (DestRC == &NVPTX::Int64RegsRegClass) in copyPhysReg()
58 else if (DestRC == &NVPTX::Float64RegsRegClass) in copyPhysReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 389 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
394 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
397 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
584 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
594 if (DestRC != RC) { in ListScheduleBottomUp()
596 if (!DestRC && !NewDef) in ListScheduleBottomUp()
603 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1137 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1142 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1145 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1452 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1462 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1464 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1470 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
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| /external/llvm/lib/Target/R600/ |
| D | SIFoldOperands.cpp | 240 const TargetRegisterClass *DestRC in runOnMachineFunction() local
245 unsigned MovOp = TII->getMovOpcode(DestRC); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 2347 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
2348 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
2350 unsigned DestSub0 = MRI.createVirtualRegister(DestRC); in splitScalar64BitUnaryOp()
2361 unsigned FullDestReg = MRI.createVirtualRegister(DestRC); in splitScalar64BitUnaryOp()
2407 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
2408 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
2410 unsigned DestSub0 = MRI.createVirtualRegister(DestRC); in splitScalar64BitBinaryOp()
2425 unsigned FullDestReg = MRI.createVirtualRegister(DestRC); in splitScalar64BitBinaryOp()
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