Searched refs:DstIsDead (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 107 const bool DstIsDead = MI.getOperand(0).isDead(); in tryOrrMovk() local
110 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryOrrMovk()
172 const bool DstIsDead = MI.getOperand(0).isDead(); in tryToreplicateChunks() local
188 RegState::Define | getDeadRegState(DstIsDead && CountThree)) in tryToreplicateChunks()
212 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryToreplicateChunks()
355 const bool DstIsDead = MI.getOperand(0).isDead(); in trySequenceOfOnes() local
362 RegState::Define | getDeadRegState(DstIsDead && SingleMovk)) in trySequenceOfOnes()
378 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in trySequenceOfOnes()
524 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm() local
528 getDeadRegState(DstIsDead && Shift == LastShift)) in expandMOVImm()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 393 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD() local
397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
525 bool DstIsDead = false; in ExpandLaneOp() local
527 DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandLaneOp()
530 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
532 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
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