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/external/valgrind/none/tests/x86/
Dbug152818-x86.stdout.exp1 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 4 (EAX = 123487FD, EFLAGS = …
2 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 3 (EAX = 123487FE, EFLAGS = …
3 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 2 (EAX = 123487FF, EFLAGS = …
4 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 1 (EAX = 123487AA, EFLAGS = …
5 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 0 (EAX = 12348765, EFLAGS = …
6 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 0 (EAX = 12348765, EFLAGS = …
7 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 1 (EAX = 123487AA, EFLAGS = …
8 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 2 (EAX = 12348701, EFLAGS = …
9 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 3 (EAX = 12348702, EFLAGS = …
10 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 4 (EAX = 12348703, EFLAGS = …
[all …]
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
66 (implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>;
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
76 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
92 (implicit EFLAGS)], IIC_MUL8>, SchedLoadReg<WriteIMulLd>;
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
DX86InstrCMovSetCC.td18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
46 CondNode, EFLAGS))], IIC_CMOV16_RM>,
52 CondNode, EFLAGS))], IIC_CMOV32_RM>,
58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
59 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
84 let Uses = [EFLAGS] in {
[all …]
DX86InstrInfo.td33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
1034 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1042 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1081 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1084 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1116 let Defs = [EFLAGS] in {
1119 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1123 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1127 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
[all …]
DX86InstrCompiler.td44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
89 (implicit EFLAGS)]>;
93 let Defs = [EFLAGS] in
100 (implicit EFLAGS)]>;
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
[all …]
DX86InstrTSX.td36 let Defs = [EFLAGS] in
38 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
DX86InstrFPStack.td327 cc, EFLAGS))]>;
331 cc, EFLAGS))]>;
335 cc, EFLAGS))]>,
340 let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
349 } // Uses = [EFLAGS], Constraints = "$src1 = $dst"
549 let Defs = [EFLAGS, FPSW] in {
551 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>;
553 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>;
555 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
567 let Defs = [EFLAGS, FPSW], Uses = [ST0] in {
[all …]
/external/llvm/test/CodeGen/X86/
Dhandle-move.ll11 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-u…
28 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-u…
61 ; Move EFLAGS dead def across another def:
62 ; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
63 ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208…
Dremat-phys-dead.ll12 ; CHECK: Remat: %EAX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %AL<imp-def>
21 ; CHECK: Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
Dclobber-fi0.ll6 ; In the code below we need to copy the EFLAGS because of scheduling constraints.
7 ; When copying the EFLAGS we need to write to the stack with push/pop. This forces
Dpeep-test-2.ll6 ; EFLAGS value from the incl, however it can't be known whether the add
D2012-01-16-mfence-nosse-flags.ll14 ; clobbers EFLAGS.
D2010-03-05-EFLAGS-Redef.ll4 ; branch folding pass. That makes a complete mess of the %EFLAGS liveness, but
Dphys_subreg_coalesce-3.ll7 ; 336L %vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg15
Dcmov.ll58 ; move without recomputing EFLAGS, because the expansion of the conditional
59 ; move with control flow may clobber EFLAGS (e.g., with xor, to set the
Dmisched-crash.ll6 ; Hoisting the last use requires trimming the EFLAGS live range to the second.
Dmisched-copy.ll13 ; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp…
Dvaargs.ll21 ; Check that [EFLAGS] hasn't been pulled in.
Dpre-ra-sched.ll10 ; CHECK: Interfering reg EFLAGS
/external/strace/linux/x86_64/
Duserent.h19 { 8*EFLAGS, "8*EFL" },
/external/libunwind/src/x86/
Dunwind_i.h45 #define EFLAGS 9 macro
Dinit.h42 c->dwarf.loc[EFLAGS] = DWARF_REG_LOC (&c->dwarf, UNW_X86_EFLAGS); in common_init()
DGget_save_loc.c48 case UNW_X86_EFLAGS: loc = c->dwarf.loc[EFLAGS]; break; in unw_get_save_loc()
DGregs.c87 case UNW_X86_EFLAGS: loc = c->dwarf.loc[EFLAGS]; break; in tdep_access_reg()
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h49 #define EFLAGS 144 macro

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