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Searched refs:EltSize (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/lib/Target/R600/
DSILoadStoreOptimizer.cpp67 unsigned EltSize);
70 unsigned EltSize);
79 unsigned EltSize);
84 unsigned EltSize);
163 unsigned EltSize){ in findMatchingDSInst() argument
189 if (offsetsCanBeCombined(Offset0, Offset1, EltSize)) in findMatchingDSInst()
210 unsigned EltSize) { in mergeRead2Pair() argument
227 unsigned NewOffset0 = Offset0 / EltSize; in mergeRead2Pair()
228 unsigned NewOffset1 = Offset1 / EltSize; in mergeRead2Pair()
229 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in mergeRead2Pair()
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DSIInstrInfo.cpp222 unsigned EltSize; in getLdStBaseRegImmOfs() local
224 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2; in getLdStBaseRegImmOfs()
228 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize(); in getLdStBaseRegImmOfs()
232 EltSize *= 64; in getLdStBaseRegImmOfs()
237 Offset = EltSize * Offset0; in getLdStBaseRegImmOfs()
DAMDGPUISelLowering.cpp724 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType()); in LowerConstantInitializer() local
727 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT); in LowerConstantInitializer()
1344 unsigned EltSize = MemEltVT.getStoreSize(); in ScalarizeVectorStore() local
1356 SrcValue.getWithOffset(i * EltSize), in ScalarizeVectorStore()
/external/llvm/lib/Transforms/Scalar/
DScalarReplAggregates.cpp423 unsigned EltSize = In->getPrimitiveSizeInBits()/8; in MergeInTypeForLoadOrStore() local
424 if (EltSize == AllocaSize) in MergeInTypeForLoadOrStore()
430 if (Offset % EltSize == 0 && AllocaSize % EltSize == 0 && in MergeInTypeForLoadOrStore()
431 (!VectorTy || EltSize == VectorTy->getElementType() in MergeInTypeForLoadOrStore()
435 VectorTy = VectorType::get(In, AllocaSize/EltSize); in MergeInTypeForLoadOrStore()
788 unsigned EltSize = DL.getTypeAllocSizeInBits(VTy->getElementType()); in ConvertScalar_ExtractValue() local
789 Elt = Offset/EltSize; in ConvertScalar_ExtractValue()
790 assert(EltSize*Elt == Offset && "Invalid modulus in validity checking"); in ConvertScalar_ExtractValue()
828 uint64_t EltSize = DL.getTypeAllocSizeInBits(AT->getElementType()); in ConvertScalar_ExtractValue() local
832 Offset+i*EltSize, nullptr, in ConvertScalar_ExtractValue()
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/external/llvm/lib/Analysis/
DConstantFolding.cpp333 uint64_t EltSize = DL.getTypeAllocSize(CS->getOperand(Index)->getType()); in ReadDataFromGlobal() local
335 if (ByteOffset < EltSize && in ReadDataFromGlobal()
364 uint64_t EltSize = DL.getTypeAllocSize(EltTy); in ReadDataFromGlobal() local
365 uint64_t Index = ByteOffset / EltSize; in ReadDataFromGlobal()
366 uint64_t Offset = ByteOffset - Index * EltSize; in ReadDataFromGlobal()
378 uint64_t BytesWritten = EltSize - Offset; in ReadDataFromGlobal()
379 assert(BytesWritten <= EltSize && "Not indexing into this element?"); in ReadDataFromGlobal()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp2077 unsigned EltSize = Size / NElts; in LowerBUILD_VECTOR() local
2079 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize); in LowerBUILD_VECTOR()
2097 Res = (Res << EltSize) | Val; in LowerBUILD_VECTOR()
2211 int EltSize = EltVT.getSizeInBits(); in LowerEXTRACT_VECTOR() local
2213 EltSize : VTN * EltSize, MVT::i64); in LowerEXTRACT_VECTOR()
2217 SDValue Offset = DAG.getConstant(C->getZExtValue() * EltSize, MVT::i32); in LowerEXTRACT_VECTOR()
2270 DAG.getConstant(EltSize, MVT::i32)); in LowerEXTRACT_VECTOR()
2299 int EltSize = EltVT.getSizeInBits(); in LowerINSERT_VECTOR() local
2301 EltSize : VTN * EltSize, MVT::i64); in LowerINSERT_VECTOR()
2304 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, MVT::i32); in LowerINSERT_VECTOR()
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/external/llvm/lib/CodeGen/
DAnalysis.cpp102 uint64_t EltSize = TLI.getDataLayout()->getTypeAllocSize(EltTy); in ComputeValueVTs() local
105 StartingOffset + i * EltSize); in ComputeValueVTs()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h378 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
382 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
DPPCISelLowering.cpp1266 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { in isSplatShuffleMask() argument
1268 (EltSize == 1 || EltSize == 2 || EltSize == 4)); in isSplatShuffleMask()
1280 for (unsigned i = 1; i != EltSize; ++i) in isSplatShuffleMask()
1284 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { in isSplatShuffleMask()
1286 for (unsigned j = 0; j != EltSize; ++j) in isSplatShuffleMask()
1295 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize, in getVSPLTImmediate() argument
1298 assert(isSplatShuffleMask(SVOp, EltSize)); in getVSPLTImmediate()
1300 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize); in getVSPLTImmediate()
1302 return SVOp->getMaskElt(0) / EltSize; in getVSPLTImmediate()
1316 unsigned EltSize = 16/N->getNumOperands(); in get_VSPLTI_elt() local
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DPPCISelDAGToDAG.cpp2910 int EltSize = N->getConstantOperandVal(1); in Select() local
2914 if (EltSize == 1) { in Select()
2919 } else if (EltSize == 2) { in Select()
2925 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!"); in Select()
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td57 int EltSize = EltVT.Size;
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
92 !if (!eq (!srl(EltSize,5),0),
95 "v" # NumElts # "f" # EltSize,
432 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
449 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
522 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
528 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
547 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
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DX86ISelLowering.cpp1384 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in X86TargetLowering() local
1397 if ( EltSize >= 32) { in X86TargetLowering()
1445 const unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in X86TargetLowering() local
1451 if (EltSize < 32) { in X86TargetLowering()
20597 unsigned EltSize = ElementType.getSizeInBits() / 8; in PerformEXTRACT_VECTOR_ELTCombine() local
20601 uint64_t Offset = EltSize * i; in PerformEXTRACT_VECTOR_ELTCombine()
/external/clang/lib/CodeGen/
DTargetInfo.cpp1980 uint64_t EltSize = getContext().getTypeSize(AT->getElementType()); in classify() local
1986 if (Size > 128 && EltSize != 256) in classify()
1989 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) { in classify()
2235 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType()); in BitsContainNoUserData() local
2241 unsigned EltOffset = i*EltSize; in BitsContainNoUserData()
2323 unsigned EltSize = TD.getTypeAllocSize(EltTy); in ContainsFloatAtOffset() local
2324 IROffset -= IROffset/EltSize*EltSize; in ContainsFloatAtOffset()
2412 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy); in GetINTEGERTypeAtOffset() local
2413 unsigned EltOffset = IROffset/EltSize*EltSize; in GetINTEGERTypeAtOffset()
DCGBuiltin.cpp1941 int EltSize = VTy->getScalarSizeInBits(); in EmitNeonRShiftImm() local
1947 if (ShiftAmt == EltSize) { in EmitNeonRShiftImm()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp1012 unsigned EltSize = EltVT.getSizeInBits() / 8; // FIXME: should be ABI size. in GetVectorElementPointer() local
1015 DAG.getConstant(EltSize, Index.getValueType())); in GetVectorElementPointer()
DLegalizeDAG.cpp598 unsigned EltSize = EltVT.getSizeInBits()/8; in PerformInsertVectorEltInMemory() local
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); in PerformInsertVectorEltInMemory()
1437 unsigned EltSize = in ExpandExtractFromVectorThroughStack() local
1440 DAG.getConstant(EltSize, Idx.getValueType())); in ExpandExtractFromVectorThroughStack()
1489 unsigned EltSize = in ExpandInsertToVectorThroughStack() local
1493 DAG.getConstant(EltSize, Idx.getValueType())); in ExpandInsertToVectorThroughStack()
DSelectionDAG.cpp122 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); in isBuildVectorAllOnes() local
124 if (CN->getAPIntValue().countTrailingOnes() < EltSize) in isBuildVectorAllOnes()
127 if (CFPN->getValueAPF().bitcastToAPInt().countTrailingOnes() < EltSize) in isBuildVectorAllOnes()
166 unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); in isBuildVectorAllZeros() local
168 if (CN->getAPIntValue().countTrailingZeros() < EltSize) in isBuildVectorAllZeros()
171 if (CFPN->getValueAPF().bitcastToAPInt().countTrailingZeros() < EltSize) in isBuildVectorAllZeros()
/external/llvm/lib/Transforms/InstCombine/
DInstructionCombining.cpp916 uint64_t EltSize = DL.getTypeAllocSize(AT->getElementType()); in FindElementAtOffset() local
917 assert(EltSize && "Cannot index into a zero-sized array"); in FindElementAtOffset()
918 NewIndices.push_back(ConstantInt::get(IntPtrTy,Offset/EltSize)); in FindElementAtOffset()
919 Offset %= EltSize; in FindElementAtOffset()
/external/clang/lib/AST/
DExprConstant.cpp1589 unsigned EltSize = Info.Ctx.getTypeSize(EltTy); in EvalAndBitcastToAPInt() local
1607 Res |= EltAsInt.zextOrTrunc(VecSize).rotr(i*EltSize+BaseEltSize); in EvalAndBitcastToAPInt()
1609 Res |= EltAsInt.zextOrTrunc(VecSize).rotl(i*EltSize); in EvalAndBitcastToAPInt()
5567 unsigned EltSize = Info.Ctx.getTypeSize(EltTy); in VisitCastExpr() local
5572 unsigned FloatEltSize = EltSize; in VisitCastExpr()
5578 Elt = SValInt.rotl(i*EltSize+FloatEltSize).trunc(FloatEltSize); in VisitCastExpr()
5580 Elt = SValInt.rotr(i*EltSize).trunc(FloatEltSize); in VisitCastExpr()
5587 Elt = SValInt.rotl(i*EltSize+EltSize).zextOrTrunc(EltSize); in VisitCastExpr()
5589 Elt = SValInt.rotr(i*EltSize).zextOrTrunc(EltSize); in VisitCastExpr()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp5062 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in LowerBUILD_VECTOR() local
5066 if (hasDominantValue && EltSize <= 32) { in LowerBUILD_VECTOR()
5146 if (EltSize >= 32) { in LowerBUILD_VECTOR()
5149 EVT EltVT = EVT::getFloatingPointVT(EltSize); in LowerBUILD_VECTOR()
5351 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in isShuffleMaskLegal() local
5352 return (EltSize >= 32 || in isShuffleMaskLegal()
5499 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in LowerVECTOR_SHUFFLE() local
5500 if (EltSize <= 32) { in LowerVECTOR_SHUFFLE()
5600 if (EltSize >= 32) { in LowerVECTOR_SHUFFLE()
5603 EVT EltVT = EVT::getFloatingPointVT(EltSize); in LowerVECTOR_SHUFFLE()
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp854 unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); in performDSPShiftCombine() local
862 EltSize, !Subtarget.isLittle()) || in performDSPShiftCombine()
863 (SplatBitSize != EltSize) || in performDSPShiftCombine()
864 (SplatValue.getZExtValue() >= EltSize)) in performDSPShiftCombine()
/external/llvm/lib/IR/
DConstants.cpp2789 unsigned EltSize = getElementByteSize(); in getSplatValue() local
2791 if (memcmp(Base, Base+i*EltSize, EltSize)) in getSplatValue()
/external/llvm/lib/Transforms/IPO/
DGlobalOpt.cpp522 uint64_t EltSize = DL.getTypeAllocSize(STy->getElementType()); in SRAGlobal() local
539 unsigned NewAlign = (unsigned)MinAlign(StartAlignment, EltSize*i); in SRAGlobal()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1770 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in isExtendedBUILD_VECTOR() local
1771 unsigned HalfSize = EltSize / 2; in isExtendedBUILD_VECTOR()
1796 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; in skipExtensionForVectorMULL() local
1798 MVT TruncVT = MVT::getIntegerVT(EltSize); in skipExtensionForVectorMULL()
6250 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in LowerVectorSRA_SRL_SHL() local
6257 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) in LowerVectorSRA_SRL_SHL()
6267 Cnt < EltSize) { in LowerVectorSRA_SRL_SHL()
/external/llvm/lib/Transforms/Instrumentation/
DMemorySanitizer.cpp832 uint32_t EltSize = DL.getTypeSizeInBits(VT->getElementType()); in getShadowTy() local
833 return VectorType::get(IntegerType::get(*MS.C, EltSize), in getShadowTy()

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