Searched refs:EvenReg (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 907 const unsigned EvenReg = CSRegs[i + 1]; in processFunctionBeforeCalleeSavedScan() local
909 AArch64::GPR64RegClass.contains(EvenReg)) ^ in processFunctionBeforeCalleeSavedScan()
911 AArch64::FPR64RegClass.contains(EvenReg)) && in processFunctionBeforeCalleeSavedScan()
915 const bool EvenRegUsed = MRI->isPhysRegUsed(EvenReg); in processFunctionBeforeCalleeSavedScan()
922 UnspilledCSGPRs.push_back(EvenReg); in processFunctionBeforeCalleeSavedScan()
925 UnspilledCSFPRs.push_back(EvenReg); in processFunctionBeforeCalleeSavedScan()
935 Reg = OddRegUsed ? EvenReg : OddReg; in processFunctionBeforeCalleeSavedScan()
940 DEBUG(dbgs() << ' ' << PrintReg(EvenReg, RegInfo)); in processFunctionBeforeCalleeSavedScan()
942 assert(((OddReg == AArch64::LR && EvenReg == AArch64::FP) || in processFunctionBeforeCalleeSavedScan()
944 RegInfo->getEncodingValue(EvenReg))) && in processFunctionBeforeCalleeSavedScan()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1481 unsigned EvenReg = MI->getOperand(0).getReg(); in FixInvalidRegPairOp() local
1483 unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false); in FixInvalidRegPairOp()
1487 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3(); in FixInvalidRegPairOp()
1519 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1526 .addReg(EvenReg, in FixInvalidRegPairOp()
1548 (TRI->regsOverlap(EvenReg, BaseReg))) { in FixInvalidRegPairOp()
1556 EvenReg, EvenDeadKill, false, in FixInvalidRegPairOp()
1560 if (OddReg == EvenReg && EvenDeadKill) { in FixInvalidRegPairOp()
1568 if (EvenReg == BaseReg) in FixInvalidRegPairOp()
1571 EvenReg, EvenDeadKill, EvenUndef, in FixInvalidRegPairOp()
[all …]
|