| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 5905 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5907 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5909 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5911 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5914 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5916 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5919 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5923 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5925 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5927 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
[all …]
|
| D | X86ISelLowering.cpp | 10580 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
10583 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
12476 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op); in EmitTest() local
12477 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp, in EmitTest()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 4123 unsigned ExtOp, TruncOp; in PromoteNode() local
4125 ExtOp = ISD::BITCAST; in PromoteNode()
4129 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4133 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
4134 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
4141 unsigned ExtOp, TruncOp; in PromoteNode() local
4144 ExtOp = ISD::BITCAST; in PromoteNode()
4147 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4150 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4155 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
|
| D | DAGCombiner.cpp | 8061 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
8063 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2916 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2922 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3006 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3012 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3019 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3073 SDNode OpNode, SDNode ExtOp, bit Commutable>
3078 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3570 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
[all …]
|
| D | ARMISelLowering.cpp | 7839 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineToVPADDL() local
7840 return DAG.getNode(ExtOp, SDLoc(N), VT, tmp); in AddCombineToVPADDL()
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 977 Value *ExtOp = getExtend(Op, WideType, IsSigned, Cmp); in WidenLoopCompare() local
978 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in WidenLoopCompare()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2149 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
2151 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr, in LowerFormalArguments()
2276 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
2278 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg, in LowerFormalArguments()
|
| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 3201 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
3205 if (ExtOp) in packTBLDVectorList()
3206 TblOps.push_back(ExtOp); in packTBLDVectorList()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4727 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
4728 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
5289 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
5290 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
|