| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.td | 51 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
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| D | AMDGPUISelLowering.h | 120 FMIN, enumerator
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| D | AMDGPUISelLowering.cpp | 133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
348 NODE_NAME_CASE(FMIN) in getTargetNodeName()
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 427 X86_INTRINSIC_DATA(avx_min_pd_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
428 X86_INTRINSIC_DATA(avx_min_ps_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
513 X86_INTRINSIC_DATA(sse2_min_pd, INTR_TYPE_2OP, X86ISD::FMIN, 0),
586 X86_INTRINSIC_DATA(sse_min_ps, INTR_TYPE_2OP, X86ISD::FMIN, 0),
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| D | X86InstrFragmentsSIMD.td | 49 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
52 // Commutative and Associative FMIN and FMAX.
286 def X86fminRnd : SDNode<"X86ISD::FMIN", SDTFPBinOpRound>;
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| D | X86ISelLowering.h | 231 FMAX, FMIN, enumerator
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| D | README-SSE.txt | 332 specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other
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| D | X86ISelLowering.cpp | 17280 case X86ISD::FMIN: in ReplaceNodeResults()
17552 case X86ISD::FMIN: return "X86ISD::FMIN"; in getTargetNodeName()
20803 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
20811 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
20820 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
20868 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
20875 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
20884 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
23124 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); in PerformFMinFMaxCombine()
23135 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break; in PerformFMinFMaxCombine()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 459 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
461 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
463 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
465 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
467 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
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| D | AArch64ISelLowering.h | 66 FMIN, enumerator
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| D | AArch64ISelLowering.cpp | 804 case AArch64ISD::FMIN: return "AArch64ISD::FMIN"; in getTargetNodeName()
3722 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS); in LowerSELECT_CC()
7820 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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| D | AArch64InstrInfo.td | 168 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
2424 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2729 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1111 FMIN = FPDataProcessing2SourceFixed | 0x00005000, enumerator
1112 FMIN_s = FMIN,
1113 FMIN_d = FMIN | FP64,
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| D | disasm-arm64.cc | 1024 FORMAT(FMIN, "fmin"); in VisitFPDataProcessing2Source()
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| D | assembler-arm64.cc | 1886 FPDataProcessing2Source(fd, fn, fm, FMIN); in fmin()
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1204 FMIN = FPDataProcessing2SourceFixed | 0x00005000, enumerator
1205 FMIN_s = FMIN,
1206 FMIN_d = FMIN | FP64,
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| D | disasm-a64.cc | 1143 FORMAT(FMIN, "fmin"); in VisitFPDataProcessing2Source()
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| D | assembler-a64.cc | 3242 V(fmin, NEON_FMIN, FMIN) \
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 177 FMIN, enumerator
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| D | ARMISelLowering.cpp | 1111 case ARMISD::FMIN: return "ARMISD::FMIN"; in getTargetNodeName()
9699 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; in PerformSELECT_CCCombine()
9721 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; in PerformSELECT_CCCombine()
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| D | ARMInstrNEON.td | 593 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
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| /external/vixl/doc/ |
| D | supported-instructions.md | 2109 ### FMIN ### subsection
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