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Searched refs:FeatureBits (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/MC/
DMCSubtargetInfo.cpp25 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, ProcFeatures); in InitMCProcessorInfo()
67 FeatureBits ^= FB; in ToggleFeature()
68 return FeatureBits; in ToggleFeature()
75 FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures); in ToggleFeature()
76 return FeatureBits; in ToggleFeature()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp21 StringRef AArch64NamedImmMapper::toString(uint32_t Value, uint64_t FeatureBits, in toString() argument
24 if (Mappings[i].isValueEqual(Value, FeatureBits)) { in toString()
34 uint32_t AArch64NamedImmMapper::fromString(StringRef Name, uint64_t FeatureBits, in fromString() argument
38 if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) { in fromString()
807 AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits, in fromString() argument
813 if (SysRegMappings[i].isNameEqual(NameLower, FeatureBits)) { in fromString()
822 if (InstMappings[i].isNameEqual(NameLower, FeatureBits)) { in fromString()
851 AArch64SysReg::SysRegMapper::toString(uint32_t Bits, uint64_t FeatureBits) const { in toString()
854 if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) { in toString()
862 if (InstMappings[i].isValueEqual(Bits, FeatureBits)) { in toString()
DAArch64BaseInfo.h285 bool isNameEqual(std::string Other, uint64_t FeatureBits=~0ULL) const {
286 if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
290 bool isValueEqual(uint32_t Other, uint64_t FeatureBits=~0ULL) const {
291 if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
301 StringRef toString(uint32_t Value, uint64_t FeatureBits, bool &Valid) const;
302 uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
1195 uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
1196 std::string toString(uint32_t Bits, uint64_t FeatureBits) const;
/external/llvm/include/llvm/MC/
DMCSubtargetInfo.h45 uint64_t FeatureBits; // Feature bits for current CPU + FS variable
71 return FeatureBits; in getFeatureBits()
76 void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; } in setFeatureBits()
/external/deqp/modules/glshared/
DglsRandomUniformBlockCase.hpp43 enum FeatureBits enum
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp798 uint64_t FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
800 if (FeatureBits & ARM::FeatureMClass) { in printMSRMaskOperand()
805 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) { in printMSRMaskOperand()
837 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) { in printMSRMaskOperand()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp2154 uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction() local
2155 if ((FeatureBits & ARM::HasV8_1aOps) == 0 || in DecodeSETPANInstruction()
2156 (FeatureBits & ARM::HasV8Ops) == 0 ) in DecodeSETPANInstruction()
4080 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() in DecodeMSRMask() local
4082 if (FeatureBits & ARM::FeatureMClass) { in DecodeMSRMask()
4102 if (!(FeatureBits & ARM::HasV7Ops)) in DecodeMSRMask()
4112 if (!(FeatureBits & ARM::HasV7Ops)) { in DecodeMSRMask()
4126 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) in DecodeMSRMask()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp312 uint64_t FeatureBits = STI.getFeatureBits(); in selectArch() local
313 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch()
314 STI.setFeatureBits(FeatureBits); in selectArch()
/external/deqp/modules/gles31/functional/
Des31fSSBOLayoutTests.cpp48 enum FeatureBits enum