Searched refs:G8RC (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 352 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerDynamicAlloc() local
354 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
378 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
386 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
451 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRSpilling() local
454 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
466 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
496 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRRestore() local
499 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
511 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
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| D | PPCRegisterInfo.td | 245 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
250 let AltOrders = [(add (sub G8RC, X2), X2)];
270 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
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| D | PPCFrameLowering.cpp | 1463 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in addScavengingSpillSlot() local
1464 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
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| D | PPCInstrQPX.td | 626 (outs qfrc:$FRT), (ins G8RC:$src),
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| D | PPCInstrInfo.td | 390 def g8rc : RegisterOperand<G8RC> {
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