| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 340 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
541 let MIOperandInfo = (ops GPR, i32imm);
552 let MIOperandInfo = (ops GPR, GPR, i32imm);
563 let MIOperandInfo = (ops GPR, i32imm);
805 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
826 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
880 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
897 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
898 // the GPR is purely vestigal at this point.
919 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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| D | ARMInstrVFP.td | 124 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
141 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
152 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
164 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
177 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
248 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
255 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
262 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
613 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
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| D | ARMInstrThumb2.td | 157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
207 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
232 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
271 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
776 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
778 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
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| /external/llvm/test/CodeGen/Mips/ |
| D | fpbr.ll | 3 …march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
6 …rch=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
18 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
20 ; GPR: not $[[GPRCC]], $[[GPRCC]]
21 ; GPR: bnez $[[GPRCC]], $BB0_2
50 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
51 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
52 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
[all …]
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| D | analyzebranch.ll | 3 …ch=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR
7 …=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR
16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
17 ; 32-GPR: mthc1 $zero, $[[Z:f[0-9]]]
18 ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
19 ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
20 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
21 ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
22 ; GPR: bnez $[[GPRCC]], $BB
49 ; GPR: mtc1 $zero, $[[Z:f[0-9]]]
[all …]
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| D | mips64muldiv.ll | 4 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR
9 ; GPR - Targets with register based mul/div (i.e. MIPS32r6)
16 ; GPR: dmul $2, ${{[45]}}, ${{[45]}}
33 ; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
46 ; GPR: ddivu $2, $4, $5
56 ; GPR: ddiv $2, $4, $5
66 ; GPR: dmodu $2, $4, $5
76 ; GPR: dmod $2, $4, $5
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| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 63 let MIOperandInfo = (ops GPR, i16imm);
82 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
103 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
140 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
142 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
159 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
161 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
198 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
217 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
219 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
[all …]
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| /external/llvm/test/CodeGen/R600/ |
| D | 128bit-kernel-args.ll | 6 ; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y
7 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z
8 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W
9 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X
19 ; R600-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y
20 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z
21 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W
22 ; R600-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X
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| D | vertex-fetch-encoding.ll | 5 ; NI: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]]…
7 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]]…
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| D | literals.ll | 39 ; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
40 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
41 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
42 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
51 ; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
52 ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
53 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
54 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
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| /external/valgrind/VEX/priv/ |
| D | host_mips_defs.h | 43 #define GPR(_mode64, _enc, _ix64, _ix32) \ macro
55 ST_IN HReg hregMIPS_GPR16 ( Bool mode64 ) { return GPR(mode64, 16, 0, 0); } in hregMIPS_GPR16()
56 ST_IN HReg hregMIPS_GPR17 ( Bool mode64 ) { return GPR(mode64, 17, 1, 1); } in hregMIPS_GPR17()
57 ST_IN HReg hregMIPS_GPR18 ( Bool mode64 ) { return GPR(mode64, 18, 2, 2); } in hregMIPS_GPR18()
58 ST_IN HReg hregMIPS_GPR19 ( Bool mode64 ) { return GPR(mode64, 19, 3, 3); } in hregMIPS_GPR19()
59 ST_IN HReg hregMIPS_GPR20 ( Bool mode64 ) { return GPR(mode64, 20, 4, 4); } in hregMIPS_GPR20()
60 ST_IN HReg hregMIPS_GPR21 ( Bool mode64 ) { return GPR(mode64, 21, 5, 5); } in hregMIPS_GPR21()
61 ST_IN HReg hregMIPS_GPR22 ( Bool mode64 ) { return GPR(mode64, 22, 6, 6); } in hregMIPS_GPR22()
63 ST_IN HReg hregMIPS_GPR12 ( Bool mode64 ) { return GPR(mode64, 12, 7, 7); } in hregMIPS_GPR12()
64 ST_IN HReg hregMIPS_GPR13 ( Bool mode64 ) { return GPR(mode64, 13, 8, 8); } in hregMIPS_GPR13()
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| D | host_ppc_defs.h | 48 #define GPR(_mode64, _enc, _ix64, _ix32) \ macro
60 ST_IN HReg hregPPC_GPR3 ( Bool mode64 ) { return GPR(mode64, 3, 0, 0); } in hregPPC_GPR3()
61 ST_IN HReg hregPPC_GPR4 ( Bool mode64 ) { return GPR(mode64, 4, 1, 1); } in hregPPC_GPR4()
62 ST_IN HReg hregPPC_GPR5 ( Bool mode64 ) { return GPR(mode64, 5, 2, 2); } in hregPPC_GPR5()
63 ST_IN HReg hregPPC_GPR6 ( Bool mode64 ) { return GPR(mode64, 6, 3, 3); } in hregPPC_GPR6()
64 ST_IN HReg hregPPC_GPR7 ( Bool mode64 ) { return GPR(mode64, 7, 4, 4); } in hregPPC_GPR7()
65 ST_IN HReg hregPPC_GPR8 ( Bool mode64 ) { return GPR(mode64, 8, 5, 5); } in hregPPC_GPR8()
66 ST_IN HReg hregPPC_GPR9 ( Bool mode64 ) { return GPR(mode64, 9, 6, 6); } in hregPPC_GPR9()
67 ST_IN HReg hregPPC_GPR10 ( Bool mode64 ) { return GPR(mode64, 10, 7, 7); } in hregPPC_GPR10()
71 ST_IN HReg hregPPC_GPR11 ( Bool mode64 ) { return GPR(mode64, 11, 0, 8); } in hregPPC_GPR11()
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| D | host_s390_defs.c | 1505 s390_disasm(ENC3(MNM, GPR, GPR), "ar", r1, r2); in s390_emit_AR()
1515 s390_disasm(ENC3(MNM, GPR, GPR), "agr", r1, r2); in s390_emit_AGR()
1525 s390_disasm(ENC3(MNM, GPR, UDXB), "a", r1, d2, x2, b2); in s390_emit_A()
1535 s390_disasm(ENC3(MNM, GPR, SDXB), "ay", r1, dh2, dl2, x2, b2); in s390_emit_AY()
1545 s390_disasm(ENC3(MNM, GPR, SDXB), "ag", r1, dh2, dl2, x2, b2); in s390_emit_AG()
1557 s390_disasm(ENC3(MNM, GPR, INT), "afi", r1, i2); in s390_emit_AFI()
1569 s390_disasm(ENC3(MNM, GPR, INT), "agfi", r1, i2); in s390_emit_AGFI()
1579 s390_disasm(ENC3(MNM, GPR, UDXB), "ah", r1, d2, x2, b2); in s390_emit_AH()
1589 s390_disasm(ENC3(MNM, GPR, SDXB), "ahy", r1, dh2, dl2, x2, b2); in s390_emit_AHY()
1599 s390_disasm(ENC3(MNM, GPR, INT), "ahi", r1, (Int)(Short)i2); in s390_emit_AHI()
[all …]
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| /external/llvm/lib/ExecutionEngine/Orc/ |
| D | OrcTargetSupport.cpp | 63 for (const auto &GPR : GPRs) in insertResolverBlock() local
64 AsmStream << " pushq %" << GPR << "\n"; in insertResolverBlock()
91 for (const auto &GPR : make_range(GPRs.rbegin(), GPRs.rend())) in insertResolverBlock() local
92 AsmStream << " popq %" << GPR << "\n"; in insertResolverBlock()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | fpconv-vector-op-scalarize.ll | 10 ; CHECK: sbfx [[GPR:w[0-9]+]], w0, #0, #1
11 ; CHECK-NEXT: scvtf d0, [[GPR]]
20 ; CHECK: and [[GPR:w[0-9]+]], w0, #0x1
21 ; CHECK-NEXT: ucvtf d0, [[GPR]]
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| /external/lldb/source/Plugins/Process/POSIX/ |
| D | RegisterContextLinux_x86_64.cpp | 18 (offsetof(GPR, regname))
23 GetRegisterContext()[gpr_##reg].byte_size = sizeof(GPR::reg); \
70 } GPR; typedef
76 GPR gpr; // General purpose registers.
111 return sizeof(GPR); in GetGPRSize()
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| D | RegisterContextFreeBSD_x86_64.cpp | 17 (offsetof(GPR, regname))
22 GetRegisterContext()[gpr_##reg].byte_size = sizeof(GPR::reg); \
59 } GPR; typedef
76 return sizeof(GPR); in GetGPRSize()
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| /external/lldb/source/Plugins/Process/Utility/ |
| D | RegisterContextDarwin_x86_64.h | 62 struct GPR struct
138 GPRWordCount = sizeof(GPR)/sizeof(uint32_t),
150 GPR gpr;
237 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr) = 0;
246 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
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| D | RegisterContextDarwin_i386.h | 63 struct GPR struct
134 GPRWordCount = sizeof(GPR)/sizeof(uint32_t),
146 GPR gpr;
233 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr) = 0;
242 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
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| D | RegisterContextDarwin_arm.h | 110 struct GPR struct
177 GPRWordCount = sizeof(GPR)/sizeof(uint32_t),
190 GPR gpr;
288 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr) in DoReadGPR()
303 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr) = 0;
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| D | RegisterContextMach_x86_64.h | 31 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
40 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
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| D | RegisterContextMach_i386.h | 31 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
40 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
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| D | RegisterContextMach_arm.h | 32 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
44 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
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| /external/lldb/source/Plugins/Process/MacOSX-Kernel/ |
| D | RegisterContextKDP_x86_64.h | 34 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
43 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
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| D | RegisterContextKDP_i386.h | 33 DoReadGPR (lldb::tid_t tid, int flavor, GPR &gpr);
42 DoWriteGPR (lldb::tid_t tid, int flavor, const GPR &gpr);
|