| /external/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfo.h | 306 bool HasBaseReg, int64_t Scale) const;
322 bool HasBaseReg, int64_t Scale) const;
541 int64_t BaseOffset, bool HasBaseReg,
546 int64_t BaseOffset, bool HasBaseReg,
651 bool HasBaseReg, int64_t Scale) override { in isLegalAddressingMode() argument
652 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
662 bool HasBaseReg, int64_t Scale) override { in getScalingFactorCost() argument
663 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale); in getScalingFactorCost()
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| D | TargetTransformInfoImpl.h | 210 bool HasBaseReg, int64_t Scale) { in isLegalAddressingMode() argument
221 bool HasBaseReg, int64_t Scale) { in getScalingFactorCost() argument
223 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale)) in getScalingFactorCost()
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| /external/llvm/lib/Analysis/ |
| D | TargetTransformInfo.cpp | 102 bool HasBaseReg, in isLegalAddressingMode() argument
104 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
120 bool HasBaseReg, in getScalingFactorCost() argument
122 return TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
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| /external/llvm/include/llvm/CodeGen/ |
| D | BasicTTIImpl.h | 128 bool HasBaseReg, int64_t Scale) { in isLegalAddressingMode() argument
132 AM.HasBaseReg = HasBaseReg; in isLegalAddressingMode()
138 bool HasBaseReg, int64_t Scale) { in getScalingFactorCost() argument
142 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 243 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
244 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
246 HasBaseReg = false; in printLeaMemReference()
249 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
273 if (HasBaseReg) in printLeaMemReference()
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| D | X86ISelLowering.cpp | 17697 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
17719 if (AM.HasBaseReg) in isLegalAddressingMode()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 234 bool HasBaseReg; member
261 : BaseGV(nullptr), BaseOffset(0), HasBaseReg(false), Scale(0), in Formula()
354 HasBaseReg = true; in InitialMatch()
360 HasBaseReg = true; in InitialMatch()
468 if (HasBaseReg && BaseRegs.empty()) { in print()
471 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1381 bool HasBaseReg, int64_t Scale) { in isAMCompletelyFolded() argument
1384 return TTI.isLegalAddressingMode(AccessTy, BaseGV, BaseOffset, HasBaseReg, Scale); in isAMCompletelyFolded()
1396 if (Scale != 0 && HasBaseReg && BaseOffset != 0) in isAMCompletelyFolded()
1436 bool HasBaseReg, int64_t Scale) { in isAMCompletelyFolded() argument
[all …]
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| D | StraightLineStrengthReduce.cpp | 238 bool HasBaseReg = false; in isGEPFoldable() local
244 HasBaseReg = true; in isGEPFoldable()
267 BaseOffset, HasBaseReg, Scale); in isGEPFoldable()
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| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 1555 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale); in operator ==()
2741 if (AddrMode.HasBaseReg) { in MatchOperationAddr()
2746 AddrMode.HasBaseReg = true; in MatchOperationAddr()
2757 if (AddrMode.HasBaseReg) in MatchOperationAddr()
2759 AddrMode.HasBaseReg = true; in MatchOperationAddr()
2892 if (!AddrMode.HasBaseReg) { in MatchAddr()
2893 AddrMode.HasBaseReg = true; in MatchAddr()
2898 AddrMode.HasBaseReg = false; in MatchAddr()
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| D | TargetLoweringBase.cpp | 1632 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1637 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1433 bool HasBaseReg; member
1435 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 281 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
286 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 3715 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale) in isLegalAddressingMode()
3724 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1928 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3525 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 10111 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalT2ScaledAddressingMode()
10169 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalAddressingMode()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10755 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
10760 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 6764 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
|