Searched refs:INST (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/test/CodeGen/CPP/ |
| D | atomic.ll | 5 …; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, Se…
6 ; CHECK: [[INST]]->setName("inst0");
7 ; CHECK: [[INST]]->setVolatile(false);
10 …; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, Seq…
11 ; CHECK: [[INST]]->setName("inst1");
12 ; CHECK: [[INST]]->setVolatile(false);
15 …; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Mon…
16 ; CHECK: [[INST]]->setName("inst2");
17 ; CHECK: [[INST]]->setVolatile(true);
20 …; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, Acq…
[all …]
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| /external/llvm/test/Transforms/LowerAtomic/ |
| D | atomic-load.ll | 7 ; CHECK: [[INST:%[a-z0-9]+]] = load
11 ; CHECK: ret i8 [[INST]]
18 ; CHECK: [[INST:%[a-z0-9]+]] = load
23 ; CHECK: ret i8 [[INST]]
30 ; CHECK: [[INST:%[a-z0-9]+]] = load
35 ; CHECK: ret i8 [[INST]]
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| D | atomic-swap.ll | 24 ; CHECK: [[INST:%[a-z0-9]+]] = load
27 ; CHECK: ret i8 [[INST]]
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| /external/llvm/test/CodeGen/X86/ |
| D | fma.ll | 1 … < %s -mtriple=i386-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST
3 … < %s -mtriple=x86_64-apple-darwin10 -mattr=+fma,-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST
5 ; RUN: llc < %s -march=x86 -mcpu=bdver2 -mattr=-fma4 | FileCheck %s --check-prefix=CHECK-FMA-INST
9 ; CHECK-FMA-INST: vfmadd213ss
19 ; CHECK-FMA-INST: vfmadd213sd
46 ; CHECK-FMA-INST: fma3_select231ssX:
47 ; CHECK-FMA-INST: vfmadd231ss %xmm
61 ; CHECK-FMA-INST: fma3_select231pdY:
62 ; CHECK-FMA-INST: vfmadd231pd %ymm
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| /external/clang/test/CodeGenCXX/ |
| D | dllexport.cpp | 23 #define INST(func) template void func(); macro
285 INST(funcTmplDef<ExplicitInst_Exported>) in INST() function
291 INST(inlineFuncTmpl1<ExplicitInst_Exported>) in INST() function
296 INST(inlineFuncTmpl2<ExplicitInst_Exported>)
302 INST(inlineFuncTmplDecl<ExplicitInst_Exported>)
308 INST(inlineFuncTmplDef<ExplicitInst_Exported>)
316 INST(funcTmplRedecl1<ExplicitInst_Exported>)
322 INST(funcTmplRedecl2<ExplicitInst_Exported>)
328 INST(funcTmplRedecl3<ExplicitInst_Exported>)
342 INST(funcTmplFriend1<ExplicitInst_Exported>)
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_exec.h | 51 #define TGSI_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\ argument
52 ((INST)->Dst[0].Register.WriteMask & (1 << (CHAN)))
54 #define TGSI_IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\ argument
55 if (TGSI_IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
57 #define TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( INST, CHAN )\ argument
59 TGSI_IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )
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| /external/clang/test/Rewriter/ |
| D | rewrite-modern-throw.m | 40 @interface INST interface
42 INST* throw_val;
52 @implementation INST implementation
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 444 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
458 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
4635 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4643 INST,
4660 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4665 INST,
4688 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4696 INST,
4712 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4717 INST,
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| D | AArch64InstrFormats.td | 2472 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2474 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
6466 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6471 (!cast<Instruction>(INST # v2i32_indexed)
6475 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6483 (!cast<Instruction>(INST # "v4i32_indexed")
6487 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6494 (!cast<Instruction>(INST # "v2i64_indexed")
6498 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6504 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
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