Searched refs:INTEL_MSAA_LAYOUT_IMS (Results 1 – 7 of 7) sorted by relevance
1033 case INTEL_MSAA_LAYOUT_IMS: in encode_msaa()1120 case INTEL_MSAA_LAYOUT_IMS: in decode_msaa()1405 case INTEL_MSAA_LAYOUT_IMS: in texel_fetch()1496 case INTEL_MSAA_LAYOUT_IMS: in texture_lookup()1616 true_layout == INTEL_MSAA_LAYOUT_IMS); in compute_msaa_layout_for_pipeline()1624 assert(true_layout == INTEL_MSAA_LAYOUT_IMS); in compute_msaa_layout_for_pipeline()1692 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) in brw_blorp_blit_params()1774 assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS); in brw_blorp_blit_params()
115 case INTEL_MSAA_LAYOUT_IMS: in intel_miptree_create_internal()138 num_samples > 1 ? INTEL_MSAA_LAYOUT_IMS : INTEL_MSAA_LAYOUT_NONE; in intel_miptree_create_internal()308 return INTEL_MSAA_LAYOUT_IMS; in compute_msaa_layout()315 return INTEL_MSAA_LAYOUT_IMS; in compute_msaa_layout()411 if (msaa_layout == INTEL_MSAA_LAYOUT_IMS) { in intel_miptree_create_for_renderbuffer()846 INTEL_MSAA_LAYOUT_IMS); in intel_miptree_alloc_hiz()
177 case INTEL_MSAA_LAYOUT_IMS: in brw_miptree_layout()
96 layout == INTEL_MSAA_LAYOUT_IMS ? in gen7_set_surface_msaa()518 assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS); in gen7_update_renderbuffer_surface()
163 INTEL_MSAA_LAYOUT_IMS, enumerator