Searched refs:ImplicitDefs (Results 1 – 15 of 15) sorted by relevance
| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 151 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr variable
575 return ImplicitDefs; in getImplicitDefs()
580 if (!ImplicitDefs) return 0; in getNumImplicitDefs()
582 for (; ImplicitDefs[i]; ++i) /*empty*/; in getNumImplicitDefs()
599 if (const uint16_t *ImpDefs = ImplicitDefs)
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| /external/llvm/lib/CodeGen/ |
| D | MachineCSE.cpp | 455 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlock() local
551 ImplicitDefs.push_back(OldReg); in ProcessBlock()
612 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
619 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
647 ImplicitDefs.clear(); in ProcessBlock()
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| D | MachineInstr.cpp | 577 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1734 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
1759 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
1787 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
1809 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
1834 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
1856 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rf()
1882 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
1911 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrii()
1927 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
1946 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ii()
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| D | ScheduleDAGFast.cpp | 442 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
521 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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| D | ScheduleDAGSDNodes.cpp | 128 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) in CheckForPhysRegDependency()
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| D | ScheduleDAGRRList.cpp | 1199 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1327 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 337 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
366 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
369 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
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| D | CodeGenInstruction.h | 221 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
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| D | DAGISelMatcherGen.cpp | 854 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
977 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
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| D | CodeGenDAGPatterns.cpp | 1792 if (!InstInfo.ImplicitDefs.empty()) { in ApplyTypeConstraints()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 303 .addReg(II.ImplicitDefs[0])); in fastEmitInst_r()
331 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rr()
363 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rrr()
389 .addReg(II.ImplicitDefs[0])); in fastEmitInst_ri()
419 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rri()
438 .addReg(II.ImplicitDefs[0])); in fastEmitInst_i()
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.cpp | 2551 if (NewDesc.ImplicitDefs) { in addDescImplicitUseDef()
2552 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) { in addDescImplicitUseDef()
2553 unsigned Reg = NewDesc.ImplicitDefs[i]; in addDescImplicitUseDef()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1655 if (NewDesc.ImplicitDefs) in optimizeCompareInstr()
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 1296 ``TargetInstrInfo::get(opcode)::ImplicitDefs``, where ``opcode`` is the opcode
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