| /external/llvm/test/Transforms/InstCombine/ |
| D | vector-mul.ll | 6 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
8 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
15 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
17 %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
22 ; CHECK: ret <4 x i8> %InVec
24 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
26 %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
31 ; CHECK: shl <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
34 define <4 x i8> @SplatPow2Test1_i8(<4 x i8> %InVec) {
36 %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | avx2-vector-shifts.ll | 5 define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
7 …%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 …
15 define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
17 …%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
25 define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
27 …%shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16…
35 define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
37 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
45 define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
47 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
[all …]
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| D | sse2-vector-shifts.ll | 5 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
7 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
17 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
27 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
37 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
45 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
47 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 10828 SDValue InVec = N->getOperand(0); in visitINSERT_VECTOR_ELT() local
10835 return InVec; in visitINSERT_VECTOR_ELT()
10837 EVT VT = InVec.getValueType(); in visitINSERT_VECTOR_ELT()
10855 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT()
10856 && isa<ConstantSDNode>(InVec.getOperand(2))) { in visitINSERT_VECTOR_ELT()
10858 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue(); in visitINSERT_VECTOR_ELT()
10862 InVec.getOperand(0), InVal, EltNo); in visitINSERT_VECTOR_ELT()
10864 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
10865 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2)); in visitINSERT_VECTOR_ELT()
10875 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) { in visitINSERT_VECTOR_ELT()
[all …]
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| D | LegalizeVectorTypes.cpp | 1615 SDValue InVec = N->getOperand(0); in SplitVecOp_TruncateHelper() local
1616 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper()
1637 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL); in SplitVecOp_TruncateHelper()
2025 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops); in WidenVecRes_Convert() local
2027 return DAG.getNode(Opcode, DL, WidenVT, InVec); in WidenVecRes_Convert()
2028 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); in WidenVecRes_Convert()
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| D | SelectionDAGBuilder.cpp | 3091 SDValue InVec = getValue(I.getOperand(0)); in visitInsertElement() local
3096 TLI.getValueType(I.getType()), InVec, InVal, InIdx)); in visitInsertElement()
3101 SDValue InVec = getValue(I.getOperand(0)); in visitExtractElement() local
3105 TLI.getValueType(I.getType()), InVec, InIdx)); in visitExtractElement()
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 1883 SDValue InVec = N->getOperand(0); in PerformDAGCombine() local
1890 return InVec; in PerformDAGCombine()
1892 EVT VT = InVec.getValueType(); in PerformDAGCombine()
1907 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
1908 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
1909 InVec.getNode()->op_end()); in PerformDAGCombine()
1910 } else if (InVec.getOpcode() == ISD::UNDEF) { in PerformDAGCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 16236 SDValue InVec = Amt.getOperand(0); in LowerScalarVariableShift() local
16237 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in LowerScalarVariableShift()
16238 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) && in LowerScalarVariableShift()
16240 BaseShAmt = InVec.getOperand(SplatIdx); in LowerScalarVariableShift()
16241 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { in LowerScalarVariableShift()
16243 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { in LowerScalarVariableShift()
16245 BaseShAmt = InVec.getOperand(1); in LowerScalarVariableShift()
16251 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec, in LowerScalarVariableShift()
16888 SDValue InVec = Op->getOperand(0); in LowerBITCAST() local
16897 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec, in LowerBITCAST()
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | SLPVectorizer.cpp | 2178 Value *InVec = vectorizeTree(INVL); in vectorizeTree() local
2184 Value *V = Builder.CreateCast(CI->getOpcode(), InVec, VecTy); in vectorizeTree()
|